Technical Documentation - 2016-05-13 17:03:27.832760
** please refer the IEEE "White rabbit clock characteristics" doi: 10.1109/ISPCS.2016.7579514 paper for citations **
The current release of the White Rabbit Switch (WRS) in Grandmaster (GM) mode has suboptimal performance on both jitter (9ps RMS 1-100kHz) and Allan Deviation (1.4E-11 τ=1s), as presented in the last WR Workshop. The following report will briefly introduce the WRS clocking scheme, the origin of the current performance in GM mode and the improvements with some hardware modifications (done on a WRS PCB V3.4 board).
The first hardware modification allows the direct distribution of the external reference clock as Layer 1 (L1) clock without using the “SoftPLL “ (i.e. a digital implementation of the PLL used to align the WR clock - local PTP clock - to the external reference clock when operating in GM mode, or to the L1 Rx clock when operating in Boundary mode). This hardware modification achieved a measured Allan Deviation (ADEV) of 4-5E-13 τ=1s and an RMS jitter of 5.6ps.
The second hardware modification (orthogonal to the first one) keeps the SoftPLL fully working, using an external board to perform a clock synthesis currently done inside the FPGA, reaching an ADEV of 2E-12 τ=1s and an RMS jitter of 2.3ps. Since the clock alignment mechanism is independent from the mode in use (GM or Boundary), any performance limitation found in GM mode will be there also in Boundary mode.