-
Peter Jansweijer authored
When implementing gthe4 in Atrix UltraScale+ with clk_gth_i = 125 MHz the tx_out_clk_o should be 62.5 MHz. However, there is a BUG_GT in the lower instantiations that is initialized with a DIV input set to 2. This causes tx_out_clk_o to be 31.25 MHz instead of 62.5 MHz.
| Name |
Last commit
|
Last update |
|---|---|---|
| bin | ||
| board | ||
| ip_cores | ||
| modules | ||
| platform | ||
| sim | ||
| syn | ||
| testbench | ||
| top | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| .gitmodules | ||
| Manifest.py |