Is this a gthe4 wizzard bug?

When implementing gthe4 in Atrix UltraScale+ with clk_gth_i = 125 MHz the tx_out_clk_o should be 62.5 MHz. However, there is a BUG_GT in the lower instantiations that is initialized with a DIV input set to 2. This causes tx_out_clk_o to be 31.25 MHz instead of 62.5 MHz.

Is this a gthe4 wizzard bug?
When implementing gthe4 in Atrix UltraScale+ with clk_gth_i = 125 MHz the tx_out_clk_o should be 62.5 MHz. However, there is a BUG_GT in the lower instantiations that is initialized with a DIV input set to 2. This causes tx_out_clk_o to be 31.25 MHz instead of 62.5 MHz.
6d93f15c · Peter Jansweijer · 7655749b · 6d93f15c
Commit 6d93f15c authored Dec 10, 2021 by Peter Jansweijer
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gtwizard_ultrascale_2.v ...xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v +1 -1

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--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
@@ -275,7 +275,7 @@ output wire [7 : 0] rxctrl3_out;
    .C_TX_INT_DATA_WIDTH(20),
    .C_TX_LINE_RATE(1.25),
    .C_TX_MASTER_CHANNEL_IDX(0),
-    .C_TX_OUTCLK_BUFG_GT_DIV(2),
+    .C_TX_OUTCLK_BUFG_GT_DIV(1),
    .C_TX_OUTCLK_FREQUENCY(125.0000000),
    .C_TX_OUTCLK_SOURCE(2),
    .C_TX_PLL_TYPE(2),