- 11 Oct, 2018 4 commits
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Tomasz Wlostowski authored
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Maciej Lipinski authored
based on g_pcs_16bit Provide the rate of the WR Reference Clock based on the information about the width of the PCS word. It is assumed to be related: * 16bit word with 62.5MHz clock * 8bit word with 125MHz clock
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Maciej Lipinski authored
WR Streamers need to be used with WR Reference clock of 62.5MHz, adding generic to specify what ref_clk is used (125MHz by default, or 62.5MHz)
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Maciej Lipinski authored
The generic g_ref_clk_rate was dummy, i.e. never used. The module pulse_stamper is used with input reference clock (and tm_cycles_i) of 125MHz and 62.5MHz clock, in the wr_streamers. Added possibility to define what clock is used (default 125MHz or 62.5MHz). In any case, the output timestamp is of cycle period of 8ns.
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- 09 Oct, 2018 4 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 18 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 15 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 14 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Maciej Lipinski authored
no frames are transmitted/received, it only checked correctness of transmission added timeout to throw an error when no frames is received for an unacceptable time
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Grzegorz Daniluk authored
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- 13 Dec, 2017 17 commits
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Peter Jansweijer authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
updates kintex7 phy name to reflect new peter_xilinx_phys convention add clbv3 reference design files last commit also needs artix7 support in xwrc_platform_xilinx.vhd added BullsEye connections CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd CLBv3: implementation files (including bmm) CLBv3: Clean up Conflicts: platform/xilinx/xwrc_platform_xilinx.vhd
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Peter Jansweijer authored
added clbv2_ref_design files added initial clbv2_ref_design ucf file removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16 Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i) updates kintex7 phy name to reflect new peter_xilinx_phys convention last commit also needs artix7 support in xwrc_platform_xilinx.vhd CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly. CLBv2: point proper bram file CLBv2: implementation (including bmm) CLBv2 reference design cleaned CLBv2: updated (hdlmake made) Xilinx ISE project file
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Peter Jansweijer authored
(cherry picked from commit 6d689ad2)
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Peter Jansweijer authored
(cherry picked from commit 70bf1927)
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Peter Jansweijer authored
(cherry picked from commit 5f934d98)
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 12 Dec, 2017 1 commit
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Grzegorz Daniluk authored
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- 11 Dec, 2017 1 commit
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Maciej Lipinski authored
Fixed by adding missing "else statement" in CRC_WORD state. In this statement the dvalid is set LOW and no ('X') data is set. Without this, the input data remainded 0xCAFE and the input dvalid remainded HIGH, thus the escape_inserter was forcing dreq=LOW in order to stop the input data for one cycle and insert special character.
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- 08 Dec, 2017 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 06 Dec, 2017 1 commit
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Grzegorz Daniluk authored
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- 04 Dec, 2017 1 commit
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Grzegorz Daniluk authored
compiled from commit: a9add108 Merge branch 'adam-lldp-rebased' into proposed_master
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