reorganized xilinx PHY files by family and Added Artix-7 Determininstic PHY sources

(cherry picked from commit 5f934d98)

reorganized xilinx PHY files by family and Added Artix-7 Determininstic PHY sources
(cherry picked from commit 5f934d98)
ca0ea0a9 · Peter Jansweijer · Grzegorz Daniluk · cc28eacd · ca0ea0a9 · ca0ea0a9
Commit ca0ea0a9 authored May 17, 2016 by Peter Jansweijer Committed by Grzegorz Daniluk Dec 13, 2017
18 changed files
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
-files = ["gtp_bitslide.vhd",
-	"gtp_phase_align.vhd",
-	"gtp_phase_align_virtex6.vhd",
-	"gtx_reset.vhd",
-	"whiterabbitgtx_wrapper_gtx.vhd",
-#	"whiterabbitgtp_wrapper.vhd",
-	"whiterabbitgtp_wrapper_tile.vhd",
-	"whiterabbit_gtxe2_channel_wrapper_gt.vhd",	
-	"wr_gtp_phy_spartan6.vhd",
-	"wr_gtx_phy_virtex6.vhd",
-	"wr_gtx_phy_kintex7.vhd"];
+files = [
+  "gtp_bitslide.vhd",
+];
+
+if (syn_device[0:4].upper()=="XC6S"): # Spartan6
+	files.extend(["spartan6/wr_gtp_phy_spartan6.vhd",
+                "spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd",
+                "spartan6/gtp_phase_align.vhd"])
+elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
+	files.extend(["virtex6/wr_gtx_phy_virtex6.vhd",
+                "virtex6/whiterabbitgtx_wrapper_gtx.vhd",
+                "virtex6/gtp_phase_align_virtex6.vhd",
+                "virtex6/gtx_reset.vhd"])
+elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
+	files.extend(["family7-gtp/wr_gtp_phy_artix7.vhd",
+                "family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd",
+                "family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd",
+                "family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd" ]);
+elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex-7 and Virtex 585, 2000, X485)
+      syn_device[0:7].upper()=="XC7V585" or
+      syn_device[0:8].upper()=="XC7V2000" or
+      syn_device[0:8].upper()=="XC7VX485"):
+	files.extend(["family7-gtx/wr_gtx_phy_kintex7.vhd",
+                "family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]);
+#elif (syn_device[0:4].upper()=="XC7V"): # Virtex7
+#	files.extend(["family7-gth/wr_gth_phy_virtex7.vhd" ]);
+                
\ No newline at end of file
--- a/platform/xilinx/wr_gtp_phy/family7-gth/readme.txt
+++ b/platform/xilinx/wr_gtp_phy/family7-gth/readme.txt
+future GTH files are to be placed here
\ No newline at end of file
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
--- a/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_artix7.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_artix7.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
--- a/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
--- a/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
--- a/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
--- a/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity wr_gtp_phy_spec_wrapper is
-
-  generic (
-    g_simulation : integer := 0);
-
-  port(
-    sfp_ref_clk_i      : in  std_logic;
-    sfp_ref_clk_o      : out std_logic;
-    sfp_tx_data_i      : in  std_logic_vector(7 downto 0);
-    sfp_tx_k_i         : in  std_logic;
-    sfp_tx_disparity_o : out std_logic;
-    sfp_tx_enc_err_o   : out std_logic;
-    sfp_rx_rbclk_o     : out std_logic;
-    sfp_rx_data_o      : out std_logic_vector(7 downto 0);
-    sfp_rx_k_o         : out std_logic;
-    sfp_rx_enc_err_o   : out std_logic;
-    sfp_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-    sfp_rst_i          : in  std_logic;
-    sfp_loopen_i       : in  std_logic;
-
-    sfp_txn_o : out std_logic;
-    sfp_txp_o : out std_logic;
-    
-    sfp_rxn_i : in std_logic;
-    sfp_rxp_i : in std_logic;
-
-    sata0_ref_clk_i      : in  std_logic;
-    sata0_ref_clk_o      : out std_logic;
-    sata0_tx_data_i      : in  std_logic_vector(7 downto 0);
-    sata0_tx_k_i         : in  std_logic;
-    sata0_tx_disparity_o : out std_logic;
-    sata0_tx_enc_err_o   : out std_logic;
-    sata0_rx_rbclk_o     : out std_logic;
-    sata0_rx_data_o      : out std_logic_vector(7 downto 0);
-    sata0_rx_k_o         : out std_logic;
-    sata0_rx_enc_err_o   : out std_logic;
-    sata0_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-    sata0_rst_i          : in  std_logic;
-    sata0_loopen_i       : in  std_logic;
-
-    sata0_txn_o : out std_logic;
-    sata0_txp_o : out std_logic;
-    sata0_rxn_i : in  std_logic;
-    sata0_rxp_i : in  std_logic;
-
-    sata1_ref_clk_i : in  std_logic;
-    sata1_ref_clk_o : out std_logic;
-
-    sata1_tx_data_i      : in  std_logic_vector(7 downto 0);
-    sata1_tx_k_i         : in  std_logic;
-    sata1_tx_disparity_o : out std_logic;
-    sata1_tx_enc_err_o   : out std_logic;
-    sata1_rx_rbclk_o     : out std_logic;
-    sata1_rx_data_o      : out std_logic_vector(7 downto 0);
-    sata1_rx_k_o         : out std_logic;
-    sata1_rx_enc_err_o   : out std_logic;
-    sata1_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-    sata1_rst_i          : in  std_logic;
-    sata1_loopen_i       : in  std_logic;
-
-    sata1_txn_o : out std_logic;
-    sata1_txp_o : out std_logic;
-    sata1_rxn_i : in  std_logic;
-    sata1_rxp_i : in  std_logic;
-
-    fmc_ref_clk_i : in  std_logic;
-    fmc_ref_clk_o : out std_logic;
-
-    fmc_tx_data_i      : in  std_logic_vector(7 downto 0);
-    fmc_tx_k_i         : in  std_logic;
-    fmc_tx_disparity_o : out std_logic;
-    fmc_tx_enc_err_o   : out std_logic;
-    fmc_rx_rbclk_o     : out std_logic;
-    fmc_rx_data_o      : out std_logic_vector(7 downto 0);
-    fmc_rx_k_o         : out std_logic;
-    fmc_rx_enc_err_o   : out std_logic;
-    fmc_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-    fmc_rst_i          : in  std_logic;
-    fmc_loopen_i       : in  std_logic;
-
-    fmc_txn_o : out std_logic;
-    fmc_txp_o : out std_logic;
-    fmc_rxn_i : in  std_logic;
-    fmc_rxp_i : in  std_logic
-    );
-
-end wr_gtp_phy_spec_wrapper;
-
-architecture rtl of wr_gtp_phy_spec_wrapper is
-
-  component wr_gtp_phy_spartan6
-    generic (
-      g_simulation : integer);
-    port (
-      ch0_ref_clk_i      : in  std_logic;
-      ch0_ref_clk_o      : out std_logic;
-      ch0_tx_data_i      : in  std_logic_vector(7 downto 0);
-      ch0_tx_k_i         : in  std_logic;
-      ch0_tx_disparity_o : out std_logic;
-      ch0_tx_enc_err_o   : out std_logic;
-      ch0_rx_rbclk_o     : out std_logic;
-      ch0_rx_data_o      : out std_logic_vector(7 downto 0);
-      ch0_rx_k_o         : out std_logic;
-      ch0_rx_enc_err_o   : out std_logic;
-      ch0_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-      ch0_rst_i          : in  std_logic;
-      ch0_loopen_i       : in  std_logic;
-      ch1_ref_clk_i      : in  std_logic;
-      ch1_ref_clk_o      : out std_logic;
-      ch1_tx_data_i      : in  std_logic_vector(7 downto 0) := "00000000";
-      ch1_tx_k_i         : in  std_logic                    := '0';
-      ch1_tx_disparity_o : out std_logic;
-      ch1_tx_enc_err_o   : out std_logic;
-      ch1_rx_data_o      : out std_logic_vector(7 downto 0);
-      ch1_rx_rbclk_o     : out std_logic;
-      ch1_rx_k_o         : out std_logic;
-      ch1_rx_enc_err_o   : out std_logic;
-      ch1_rx_bitslide_o  : out std_logic_vector(3 downto 0);
-      ch1_rst_i          : in  std_logic                    := '0';
-      ch1_loopen_i       : in  std_logic                    := '0';
-      pad_txn0_o         : out std_logic;
-      pad_txp0_o         : out std_logic;
-      pad_rxn0_i         : in  std_logic                    := '0';
-      pad_rxp0_i         : in  std_logic                    := '0';
-      pad_txn1_o         : out std_logic;
-      pad_txp1_o         : out std_logic;
-      pad_rxn1_i         : in  std_logic                    := '0';
-      pad_rxp1_i         : in  std_logic                    := '0');
-  end component;
-  
-begin  -- rtl
-
-
-  U_GTP1 : wr_gtp_phy_spartan6
-    generic map (
-      g_simulation => g_simulation)
-    port map (
-      ch0_ref_clk_i      => fmc_ref_clk_i,
-      ch0_ref_clk_o      => fmc_ref_clk_o,
-      ch0_tx_data_i      => fmc_tx_data_i,
-      ch0_tx_k_i         => fmc_tx_k_i,
-      ch0_tx_disparity_o => fmc_tx_disparity_o,
-      ch0_tx_enc_err_o   => fmc_tx_enc_err_o,
-      ch0_rx_rbclk_o     => fmc_rx_rbclk_o,
-      ch0_rx_data_o      => fmc_rx_data_o,
-      ch0_rx_k_o         => fmc_rx_k_o,
-      ch0_rx_enc_err_o   => fmc_rx_enc_err_o,
-      ch0_rx_bitslide_o  => fmc_rx_bitslide_o,
-      ch0_rst_i          => fmc_rst_i,
-      ch0_loopen_i       => fmc_loopen_i,
-      ch1_ref_clk_i      => sata0_ref_clk_i,
-      ch1_ref_clk_o      => sata0_ref_clk_o,
-      ch1_tx_data_i      => sata0_tx_data_i,
-      ch1_tx_k_i         => sata0_tx_k_i,
-      ch1_tx_disparity_o => sata0_tx_disparity_o,
-      ch1_tx_enc_err_o   => sata0_tx_enc_err_o,
-      ch1_rx_data_o      => sata0_rx_data_o,
-      ch1_rx_rbclk_o     => sata0_rx_rbclk_o,
-      ch1_rx_k_o         => sata0_rx_k_o,
-      ch1_rx_enc_err_o   => sata0_rx_enc_err_o,
-      ch1_rx_bitslide_o  => sata0_rx_bitslide_o,
-      ch1_rst_i          => sata0_rst_i,
-      ch1_loopen_i       => sata0_loopen_i,
-      pad_txn0_o         => fmc_txn_o,
-      pad_txp0_o         => fmc_txp_o,
-      pad_rxn0_i         => fmc_rxn_i,
-      pad_rxp0_i         => fmc_rxp_i,
-      pad_txn1_o         => sata0_txn_o,
-      pad_txp1_o         => sata0_txp_o,
-      pad_rxn1_i         => sata0_rxn_i,
-      pad_rxp1_i         => sata0_rxp_i);
-
-
-  U_GTP2 : wr_gtp_phy_spartan6
-    generic map (
-      g_simulation => g_simulation)
-    port map (
-      ch0_ref_clk_i      => sata1_ref_clk_i,
-      ch0_ref_clk_o      => sata1_ref_clk_o,
-      ch0_tx_data_i      => sata1_tx_data_i,
-      ch0_tx_k_i         => sata1_tx_k_i,
-      ch0_tx_disparity_o => sata1_tx_disparity_o,
-      ch0_tx_enc_err_o   => sata1_tx_enc_err_o,
-      ch0_rx_rbclk_o     => sata1_rx_rbclk_o,
-      ch0_rx_data_o      => sata1_rx_data_o,
-      ch0_rx_k_o         => sata1_rx_k_o,
-      ch0_rx_enc_err_o   => sata1_rx_enc_err_o,
-      ch0_rx_bitslide_o  => sata1_rx_bitslide_o,
-      ch0_rst_i          => sata1_rst_i,
-      ch0_loopen_i       => sata1_loopen_i,
-
-      ch1_ref_clk_i      => sfp_ref_clk_i,
-      ch1_ref_clk_o      => sfp_ref_clk_o,
-      ch1_tx_data_i      => sfp_tx_data_i,
-      ch1_tx_k_i         => sfp_tx_k_i,
-      ch1_tx_disparity_o => sfp_tx_disparity_o,
-      ch1_tx_enc_err_o   => sfp_tx_enc_err_o,
-      ch1_rx_data_o      => sfp_rx_data_o,
-      ch1_rx_rbclk_o     => sfp_rx_rbclk_o,
-      ch1_rx_k_o         => sfp_rx_k_o,
-      ch1_rx_enc_err_o   => sfp_rx_enc_err_o,
-      ch1_rx_bitslide_o  => sfp_rx_bitslide_o,
-      ch1_rst_i          => sfp_rst_i,
-      ch1_loopen_i       => sfp_loopen_i,
-      pad_txn0_o         => sata1_txn_o,
-      pad_txp0_o         => sata1_txp_o,
-      pad_rxn0_i         => sata1_rxn_i,
-      pad_rxp0_i         => sata1_rxp_i,
-      pad_txn1_o         => sfp_txn_o,
-      pad_txp1_o         => sfp_txp_o,
-      pad_rxn1_i         => sfp_rxn_i,
-      pad_rxp1_i         => sfp_rxp_i);
-
-end rtl;