Merge branch 'peter_lpdc_via_wishbone_mdio' into 'wrpc-v5'

Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio See merge request !9

Merge branch 'peter_lpdc_via_wishbone_mdio' into 'wrpc-v5'
Update family7 gtx-lp and gthe4-lp, now using lpdc via wishbone mdio See merge request !9
d7c7b52e · Tristan Gingold · bb25c738 · 0e3962b4 · d7c7b52e · d7c7b52e
Commit d7c7b52e authored Dec 11, 2023 by Tristan Gingold
10 changed files
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
@@ -51,15 +51,24 @@ xilinx_ip_common = [
 ];

 xilinx_ip_gthe4_lp = [
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_top.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.xdc",
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_gthe4.v",
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_v1_7_gthe4_channel.v"
 ];

+xilinx_ip_gthe4_lp_125 = [
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_ooc.xdc",
+];
+
+xilinx_ip_gthe4_lp_100 = [
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc",
+];
+
 xilinx_ip_gthe4_common_lp = [
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
@@ -162,6 +171,15 @@ elif (syn_device[0:6].upper()=="XCAU10" or # Artix Ultrascale+ AU10P AU15P GTH
    files.extend([
        "family7-gthe4-lp/wr_gthe4_phy_family7_lp.vhd",
        "family7-gtx-lp/gtx_comma_detect_lp.vhd",
+        "common/lpdc_mdio_regs.vhd",
        ]);
-    files.extend( xilinx_ip_gthe4_lp );        # Note that gthe4 depend on Vivado version
-    files.extend( xilinx_ip_gthe4_common_lp ); # and instantiate its specific common files 
+    files.extend( xilinx_ip_gthe4_lp );             # Note that gthe4 depend on Vivado version
+    files.extend( xilinx_ip_gthe4_common_lp );      # and instantiate its specific common files 
+    # PHY reference clock defaults to 125 MHz; check if 100 MHz is defined
+    try:
+        if (phy_ref_clk=="100"):
+            files.extend( xilinx_ip_gthe4_lp_100 );
+        else:
+            files.extend( xilinx_ip_gthe4_lp_125 ); # if phy_clk_ref exists but is other than "100"
+    except:
+        files.extend( xilinx_ip_gthe4_lp_125 );     # if phy_clk_ref does not exists
--- a/platform/xilinx/wr_gtp_phy/family7-gthe4-lp/wr_gthe4_phy_family7_lp.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gthe4-lp/wr_gthe4_phy_family7_lp.vhd
@@ -6,7 +6,7 @@
 -- Author     : Peter Jansweijer, Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2013-04-08
-- Last update: 2023-01-27
+-- Last update: 2023-06-06
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -37,6 +37,7 @@
 -- Revisions  :
 -- Date        Version  Author    Description
 -- 2013-04-08  0.1      PeterJ    Initial release based on "wr_gtx_phy_virtex6.vhd" and "wr_gtx_phy_family7_lp.vhd"
+-- 2013-06-06  0.2      PeterJ    use WB bus for LPDC regs
 -------------------------------------------------------------------------------

 library ieee;
@@ -48,6 +49,8 @@ use unisim.vcomponents.all;

 use work.gencores_pkg.all;
 use work.disparity_gen_pkg.all;
+use work.wishbone_pkg.all;
+use work.lpdc_mdio_regs_pkg.all;

 entity wr_gthe4_phy_family7_lp is

@@ -65,6 +68,10 @@ entity wr_gthe4_phy_family7_lp is
    -- Note: DMTD clock is also used as free running clock
    clk_dmtd_i           : in std_logic;

+    -- systemc clock for MDIO registers
+    clk_sys_i            : in std_logic;
+    rst_sys_n_i          : in std_logic;
+
    -- TX path, synchronous to tx_out_clk_o (62.5 MHz):
    tx_out_clk_o         : out std_logic;
    tx_locked_o          : out std_logic;
@@ -113,16 +120,16 @@ entity wr_gthe4_phy_family7_lp is
    loopen_i             : in std_logic;
    tx_prbs_sel_i        : in std_logic_vector(2 downto 0);
    
-    lpc_ctrl_i           : in  std_logic_vector(15 downto 0);
-    lpc_stat_o           : out std_logic_vector(15 downto 0);
-
    pad_txn_o            : out std_logic;
    pad_txp_o            : out std_logic;

    pad_rxn_i            : in std_logic := '0';
    pad_rxp_i            : in std_logic := '0';

-    rdy_o                : out std_logic
+    rdy_o                : out std_logic;
+
+    mdio_slave_i         : in  t_wishbone_slave_in;
+    mdio_slave_o         : out t_wishbone_slave_out
    );
 end wr_gthe4_phy_family7_lp;

@@ -229,7 +236,7 @@ architecture rtl of wr_gthe4_phy_family7_lp is
  signal tx_out_clk                    : std_logic;
  signal tx_out_clk_sampled            : std_logic;
  signal rx_rec_clk                    : std_logic;
-  signal rx_rec_clk_sampled : std_logic;
+  signal rx_rec_clk_sampled            : std_logic;

  signal serdes_ready_a                : std_logic;
  signal serdes_ready_txclk            : std_logic;
@@ -253,42 +260,38 @@ architecture rtl of wr_gthe4_phy_family7_lp is
  signal cur_disp                      : t_8b10b_disparity;

  signal tx_data_8b10b                 : std_logic_vector(19 downto 0);
-  
-  signal tx_sw_reset        : std_logic;
-  signal tx_enable          : std_logic;
+
  signal tx_enable_txclk    : std_logic;
-  signal rx_enable          : std_logic;
-  signal rx_sw_reset        : std_logic;
-  signal cpll_sw_reset      : std_logic;
-  signal cd_reset           : std_logic;

  signal gth_tx_reset_a     : std_logic;
  signal gth_rx_reset_a     : std_logic;
  
  signal gth_loopback       : std_logic_vector(2 downto 0) := "000";
-  signal comma_target_pos   : std_logic_vector(4 downto 0);
-  signal comma_current_pos  : std_logic_vector(4 downto 0);
  signal rx_data_raw        : std_logic_vector(19 downto 0);
  signal rx_data_decode     : std_logic_vector(19 downto 0);
  signal rx_code_err        : std_logic_vector(1 downto 0);

-  signal link_up            : std_logic;
-  signal link_aligned       : std_logic;
  signal tx_rst_done        : std_logic;
  signal txusrpll_locked    : std_logic;
  signal rx_rst_done        : std_logic;
-  signal comma_pos_valid    : std_logic;
-  signal txresetdone        : std_logic;
-  signal rxresetdone        : std_logic;
+
+  signal lpdc_regs_out      : t_lpdc_regs_master_out;
+  signal lpdc_regs_in       : t_lpdc_regs_master_in;
+  signal drp_regs_in        : t_wishbone_slave_out;
+  signal drp_regs_out       : t_wishbone_slave_in;

 begin

-  tx_sw_reset    <= lpc_ctrl_i(0);
-  tx_enable      <= lpc_ctrl_i(1); -- Not used. Tx enabled after tx_out_clk synced rst_n
-  rx_enable      <= lpc_ctrl_i(2); -- Not used. Rx enables after serdes_ready_rxclk
-  rx_sw_reset    <= lpc_ctrl_i(3);
-  cpll_sw_reset  <= lpc_ctrl_i(4); -- Not used. cpll reset already incorporated in tx_sw_reset
-  cd_reset       <= lpc_ctrl_i(5);
+  U_LPDC_regs : entity work.lpdc_mdio_regs
+    port map (
+      rst_n_i     => rst_sys_n_i,
+      clk_i       => clk_sys_i,
+      wb_i        => mdio_slave_i,
+      wb_o        => mdio_slave_o,
+      lpdc_regs_i => lpdc_regs_in,
+      lpdc_regs_o => lpdc_regs_out,
+      drp_regs_i  => drp_regs_in,
+      drp_regs_o  => drp_regs_out);

  -- Near-end PMA loopback if loopen_i active
  gth_loopback <= "010" when loopen_i = '1' else "000";
@@ -298,7 +301,7 @@ begin
    (
      clk_i    => clk_dmtd_i,
      rst_n_i  => '1',
-      data_i   => tx_sw_reset,
+      data_i   => lpdc_regs_out.CTRL_tx_sw_reset,
      synced_o => gth_tx_reset_a
      );

@@ -307,7 +310,7 @@ begin
    (
      clk_i    => tx_out_clk,
      rst_n_i  => '1',
-      data_i   => tx_enable,
+      data_i   => lpdc_regs_out.CTRL_tx_enable,
      synced_o => tx_enable_txclk
      );

@@ -316,7 +319,7 @@ begin
    (
      clk_i    => clk_dmtd_i,
      rst_n_i  => '1',
-      data_i   => rx_sw_reset,
+      data_i   => lpdc_regs_out.CTRL_rx_sw_reset,
      synced_o => gth_rx_reset_a
      );

@@ -340,11 +343,9 @@ begin
      clk_dmtd_i    => clk_dmtd_i,
      clk_sampled_o => tx_out_clk_sampled);

-  comma_target_pos <= lpc_ctrl_i(13 downto 13 - 4);
-
-  process(rx_rec_clk_sampled, tx_out_clk_sampled, lpc_ctrl_i)
+  process(rx_rec_clk_sampled, tx_out_clk_sampled, lpdc_regs_out)
  begin
-    case lpc_ctrl_i(15 downto 14) is
+    case lpdc_regs_out.CTRL_dmtd_clk_sel is
      when "00" =>
        clk_sampled_o <= rx_rec_clk_sampled;
      when "01" =>
@@ -354,8 +355,6 @@ begin
    end case;
  end process;

-  tx_enc_err_o <= '0';
-
  U_SyncReset : gc_sync_ffs
    port map
    (
@@ -512,21 +511,21 @@ begin
      rst_n_i  => '1',
      data_i   => serdes_ready_a,
      synced_o => serdes_ready_txclk);
-  
+
  U_Comma_Detect : gtx_comma_detect_lp
    generic map(
      g_id => 0
      )
    port map (
      clk_rx_i            => rx_rec_clk,
-      rst_i               => cd_reset,
+      rst_i               => lpdc_regs_out.CTRL_aux_reset,
      rx_data_raw_i       => rx_data_raw,
      rx_data_raw_o       => rx_data_decode,
-      comma_target_pos_i  => comma_target_pos,
-      comma_current_pos_o => comma_current_pos,
-      comma_pos_valid_o   => comma_pos_valid,
-      link_up_o           => link_up,
-      aligned_o           => link_aligned);
+      comma_target_pos_i  => lpdc_regs_out.CTRL_comma_target_pos(4 downto 0),
+      comma_current_pos_o => lpdc_regs_in.STAT_comma_current_pos(4 downto 0),
+      comma_pos_valid_o   => lpdc_regs_in.STAT_comma_pos_valid,
+      link_up_o           => lpdc_regs_in.STAT_link_up,
+      aligned_o           => lpdc_regs_in.STAT_link_aligned);

  U_Sync_RxReset : gc_sync_ffs
    port map (
@@ -555,19 +554,10 @@ begin
      rdisp_err_o => open,
      out_8b_o    => rx_data_int(7 downto 0));

-  lpc_stat_o(0)           <= '1';               -- Not used. Signal cpll_locked
-  lpc_stat_o(1)           <= link_up;
-  lpc_stat_o(2)           <= link_aligned;
-  lpc_stat_o(3)           <= tx_rst_done;
-  lpc_stat_o(4)           <= '1';               -- Not used. Signal txusrpll_locked
-  lpc_stat_o(5)           <= rx_rst_done;
-  
-  lpc_stat_o(13 downto 9) <= comma_current_pos;
-  lpc_stat_o(14)          <= comma_pos_valid;
-
-  -- Debug not used:
-  lpc_stat_o(6)           <= '0';
-  lpc_stat_o(15)          <= '0';
+  lpdc_regs_in.STAT_pll_locked  <= '1';         -- Not used. Signal pll_locked
+  lpdc_regs_in.STAT_txusrpll_locked <= '1';     -- Not used. Signal pll_locked
+  lpdc_regs_in.STAT_tx_rst_done <= tx_rst_done;
+  lpdc_regs_in.STAT_rx_rst_done <= rx_rst_done;

  p_gen_rx_outputs : process(rx_rec_clk, rst_rxclk_n)
  begin

--- a/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc
+#------------------------------------------------------------------------------
+#  (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
+#
+#  This file contains confidential and proprietary information
+#  of Xilinx, Inc. and is protected under U.S. and
+#  international copyright and other intellectual property
+#  laws.
+#
+#  DISCLAIMER
+#  This disclaimer is not a license and does not grant any
+#  rights to the materials distributed herewith. Except as
+#  otherwise provided in a valid license issued to you by
+#  Xilinx, and to the maximum extent permitted by applicable
+#  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+#  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+#  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+#  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+#  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+#  (2) Xilinx shall not be liable (whether in contract or tort,
+#  including negligence, or under any other theory of
+#  liability) for any loss or damage of any kind or nature
+#  related to, arising under or in connection with these
+#  materials, including for any direct, or any indirect,
+#  special, incidental, or consequential loss or damage
+#  (including loss of data, profits, goodwill, or any type of
+#  loss or damage suffered as a result of any action brought
+#  by a third party) even if such damage or loss was
+#  reasonably foreseeable or Xilinx had been advised of the
+#  possibility of the same.
+#
+#  CRITICAL APPLICATIONS
+#  Xilinx products are not designed or intended to be fail-
+#  safe, or for use in any application requiring fail-safe
+#  performance, such as life-support or safety devices or
+#  systems, Class III medical devices, nuclear facilities,
+#  applications related to the deployment of airbags, or any
+#  other applications that could lead to death, personal
+#  injury, or severe property or environmental damage
+#  (individually and collectively, "Critical
+#  Applications"). Customer assumes the sole risk and
+#  liability of any use of Xilinx products in Critical
+#  Applications, subject only to applicable laws and
+#  regulations governing limitations on product liability.
+#
+#  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+#  PART OF THIS FILE AT ALL TIMES.
+#------------------------------------------------------------------------------
+
+
+# UltraScale FPGAs Transceivers Wizard IP core-level XDC file for out-of-context flows
+# ----------------------------------------------------------------------------------------------------------------------
+
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs.
+
+# Free-running clock constraint
+create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
+
+# CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
+create_clock -period 10.0 [get_ports gtrefclk0_in[0]]
+
+# DRP clock constraint for CHANNEL primitive
+create_clock -period 16.0 [get_ports drpclk_in[0]]
+
+
+##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
+
+# False path constraints
+# ----------------------------------------------------------------------------------------------------------------------
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}] -quiet
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}] -quiet
+
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -35,6 +35,7 @@ use ieee.std_logic_1164.all;

 library work;
 use work.endpoint_pkg.all;
+use work.wishbone_pkg.all;

 package wr_xilinx_pkg is

@@ -238,12 +239,13 @@ package wr_xilinx_pkg is
  component wr_gtx_phy_family7_lp is
  generic (
    -- set to non-zero value to speed up the simulation by reducing some delays
-    g_simulation     : integer := 0;
-    g_id             : integer := 0);
+    g_simulation     : integer := 0);
  port (
    clk_gtx_i        : in std_logic;
    clk_dmtd_i       : in std_logic;
    clk_ref_i        : in std_logic;
+    clk_sys_i        : in std_logic;
+    rst_sys_n_i      : in std_logic;
    tx_out_clk_o     : out std_logic;
    tx_locked_o      : out std_logic;
    tx_data_i        : in std_logic_vector(15 downto 0);
@@ -264,8 +266,8 @@ package wr_xilinx_pkg is
    pad_rxn_i        : in std_logic := '0';
    pad_rxp_i        : in std_logic := '0';
    rdy_o            : out std_logic;
-    lpc_ctrl_i       : in  std_logic_vector(15 downto 0) := x"0000";
-    lpc_stat_o       : out std_logic_vector(15 downto 0);
+    mdio_slave_i     : in  t_wishbone_slave_in;
+    mdio_slave_o     : out t_wishbone_slave_out;
    fmon_clk_tx_o    : out std_logic;
    fmon_clk_tx2_o   : out std_logic;
    fmon_clk_rx_o    : out std_logic);
@@ -335,6 +337,8 @@ package wr_xilinx_pkg is
  port (
    clk_gth_i            : in std_logic;
    clk_dmtd_i           : in std_logic;
+    clk_sys_i            : in std_logic;
+    rst_sys_n_i          : in std_logic;
    tx_out_clk_o         : out std_logic;
    tx_locked_o          : out std_logic;
    tx_data_i            : in std_logic_vector(15 downto 0);
@@ -350,13 +354,13 @@ package wr_xilinx_pkg is
    rst_i                : in std_logic;
    loopen_i             : in std_logic;
    tx_prbs_sel_i        : in std_logic_vector(2 downto 0);
-    lpc_ctrl_i           : in  std_logic_vector(15 downto 0) := x"0000";
-    lpc_stat_o           : out std_logic_vector(15 downto 0);
    pad_txn_o            : out std_logic;
    pad_txp_o            : out std_logic;
    pad_rxn_i            : in std_logic := '0';
    pad_rxp_i            : in std_logic := '0';
-    rdy_o                : out std_logic
+    rdy_o                : out std_logic;
+    mdio_slave_i         : in  t_wishbone_slave_in;
+    mdio_slave_o         : out t_wishbone_slave_out
    );
  end component;