GTHE4_lp 125 / 100 MHz PHY Reference Clock selection

0e3962b4 · Peter Jansweijer · 0c342bd3 · 0e3962b4 · 0e3962b4 · 0e3962b4
Commit 0e3962b4 authored Aug 29, 2023 by Peter Jansweijer
7 changed files
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
@@ -51,15 +51,24 @@ xilinx_ip_common = [
 ];

 xilinx_ip_gthe4_lp = [
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_top.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.xdc",
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gtwizard_gthe4.v",
-    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc",
    "xilinx-ip/gthe4_lp/gtwizard_ultrascale_v1_7_gthe4_channel.v"
 ];

+xilinx_ip_gthe4_lp_125 = [
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_125/gtwizard_ultrascale_2_ooc.xdc",
+];
+
+xilinx_ip_gthe4_lp_100 = [
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
+    "xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc",
+];
+
 xilinx_ip_gthe4_common_lp = [
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "xilinx-ip/gthe4_lp/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
@@ -164,5 +173,13 @@ elif (syn_device[0:6].upper()=="XCAU10" or # Artix Ultrascale+ AU10P AU15P GTH
        "family7-gtx-lp/gtx_comma_detect_lp.vhd",
        "common/lpdc_mdio_regs.vhd",
        ]);
-    files.extend( xilinx_ip_gthe4_lp );        # Note that gthe4 depend on Vivado version
-    files.extend( xilinx_ip_gthe4_common_lp ); # and instantiate its specific common files 
+    files.extend( xilinx_ip_gthe4_lp );             # Note that gthe4 depend on Vivado version
+    files.extend( xilinx_ip_gthe4_common_lp );      # and instantiate its specific common files 
+    # PHY reference clock defaults to 125 MHz; check if 100 MHz is defined
+    try:
+        if (phy_ref_clk=="100"):
+            files.extend( xilinx_ip_gthe4_lp_100 );
+        else:
+            files.extend( xilinx_ip_gthe4_lp_125 ); # if phy_clk_ref exists but is other than "100"
+    except:
+        files.extend( xilinx_ip_gthe4_lp_125 );     # if phy_clk_ref does not exists
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/phy_ref_clk_100/gtwizard_ultrascale_2_ooc.xdc
+#------------------------------------------------------------------------------
+#  (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
+#
+#  This file contains confidential and proprietary information
+#  of Xilinx, Inc. and is protected under U.S. and
+#  international copyright and other intellectual property
+#  laws.
+#
+#  DISCLAIMER
+#  This disclaimer is not a license and does not grant any
+#  rights to the materials distributed herewith. Except as
+#  otherwise provided in a valid license issued to you by
+#  Xilinx, and to the maximum extent permitted by applicable
+#  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+#  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+#  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+#  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+#  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+#  (2) Xilinx shall not be liable (whether in contract or tort,
+#  including negligence, or under any other theory of
+#  liability) for any loss or damage of any kind or nature
+#  related to, arising under or in connection with these
+#  materials, including for any direct, or any indirect,
+#  special, incidental, or consequential loss or damage
+#  (including loss of data, profits, goodwill, or any type of
+#  loss or damage suffered as a result of any action brought
+#  by a third party) even if such damage or loss was
+#  reasonably foreseeable or Xilinx had been advised of the
+#  possibility of the same.
+#
+#  CRITICAL APPLICATIONS
+#  Xilinx products are not designed or intended to be fail-
+#  safe, or for use in any application requiring fail-safe
+#  performance, such as life-support or safety devices or
+#  systems, Class III medical devices, nuclear facilities,
+#  applications related to the deployment of airbags, or any
+#  other applications that could lead to death, personal
+#  injury, or severe property or environmental damage
+#  (individually and collectively, "Critical
+#  Applications"). Customer assumes the sole risk and
+#  liability of any use of Xilinx products in Critical
+#  Applications, subject only to applicable laws and
+#  regulations governing limitations on product liability.
+#
+#  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+#  PART OF THIS FILE AT ALL TIMES.
+#------------------------------------------------------------------------------
+
+
+# UltraScale FPGAs Transceivers Wizard IP core-level XDC file for out-of-context flows
+# ----------------------------------------------------------------------------------------------------------------------
+
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs.
+
+# Free-running clock constraint
+create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
+
+# CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
+create_clock -period 10.0 [get_ports gtrefclk0_in[0]]
+
+# DRP clock constraint for CHANNEL primitive
+create_clock -period 16.0 [get_ports drpclk_in[0]]
+
+
+##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]] -quiet
+set_false_path -to [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]] -quiet
+
+# False path constraints
+# ----------------------------------------------------------------------------------------------------------------------
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}] -quiet
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}] -quiet
+
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc