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White Rabbit core collection
Commit bb25c738 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'wrpc-v5-sim-works' into 'wrpc-v5' 

wrc_core sim for wrpc-v5 works

See merge request !10
parents 89fd975c 296c17cc
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    board/spec/xwrc_board_spec.vhd
    View file @ bb25c738
    ......@@ -73,6 +73,7 @@ entity xwrc_board_spec is
    g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
    -- memory initialisation file for embedded CPU
    g_dpram_initf : string := "default_xilinx";
    g_dpram_size : integer := 144*1024/4;
    -- identification (id and ver) of the layout of words in the generic diag interface
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    ......@@ -449,7 +450,7 @@ begin -- architecture struct
    g_ep_rxbuf_size => 1024,
    g_tx_runt_padding => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_dpram_size => 144*1024/4,
    g_dpram_size => g_dpram_size,
    g_interface_mode => PIPELINED,
    g_address_granularity => BYTE,
    g_aux_sdb => g_aux_sdb,
    ......
    modules/wrc_core/wrc_urv_wrapper.vhd
    View file @ bb25c738
    ......@@ -127,7 +127,7 @@ begin
    dwb_o <= dwb_out;
    U_cpu_core : urv_cpu
    U_cpu_core : entity work.urv_cpu
    generic map (
    g_with_hw_debug => 1,
    g_with_hw_mulh => 1,
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/Manifest.py
    View file @ bb25c738
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    #sim_tool="modelsim"
    sim_tool="riviera"
    top_module="main"
    fetchto="../../ip_cores"
    vlog_opt="+incdir+../../../sim +incdir"
    vcom_opt="-relax -packagevhdlsv"
    include_dirs = ["../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src" ]
    modules = { "local" : ["../../..",
    ......@@ -16,6 +8,6 @@ modules = { "local" : ["../../..",
    "../../../ip_cores/general-cores",
    "../../../ip_cores/urv-core"]}
    files = ["main.sv","synthesis_descriptor.vhd"]
    files = ["synthesis_descriptor.vhd"]
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/Manifest.py 0 → 100644
    View file @ bb25c738
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    sim_tool="modelsim"
    top_module="main"
    vcom_opt="-mixedsvvh"
    include_dirs = [ "../" ]
    modules = {
    "local" : [ "../" ]
    }
    files = [ "main.sv" ]
    \ No newline at end of file
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/main.sv 0 → 100644
    View file @ bb25c738
    //
    // White Rabbit Core Hands-On Course
    //
    // Lesson 04a: Trivial streamer demo
    //
    // Objectives:
    // - Demonstrate pulse distribution example on a simulation
    //
    // Brief description:
    // Testbench instantiates two SPEC cards connected to each other via a Gigabit
    // Ethernet link. SPEC A sends input trigger pulses to SPEC B, which reproduces them with
    // fixed, 20us delay.
    `timescale 10fs/10fs // need very fine timestep to correctly simulate the GTP.
    module main;
    // Parameters
    // Reference clock period.
    parameter g_ref_clock_period = 8ns;
    reg clk_20m = 0, clk_ref = 0;
    wire uart_txd;
    wire [7:0] uart_data;
    wire uart_data_valid;
    // Generate the reference clock
    always #(g_ref_clock_period / 2) clk_ref <= ~clk_ref;
    // Generate the 20 MHz VCXO clock
    always #(50ns / 2) clk_20m <= ~clk_20m;
    reg pulse_in = 0;
    wire pulse_out;
    wire [4:0] dio_out_b;
    // This time we have two SPECs talking to each other in the same testbench
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_A (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    .clk_125m_gtp_p_i (clk_ref),
    .clk_125m_gtp_n_i (~clk_ref),
    .clk_20m_vcxo_i(clk_20m),
    // Connect the gigabit output of one SPEC with the RX input of the other,
    // and vice-versa.
    .sfp_txp_o(a_to_b_p),
    .sfp_txn_o(a_to_b_n),
    .sfp_rxp_i(b_to_a_p),
    .sfp_rxn_i(b_to_a_n),
    .dio_p_i( {3'b0, pulse_in, 1'b0} ),
    .dio_n_i( {3'b1, ~pulse_in, 1'b1} )
    );
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_B (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    .clk_125m_gtp_p_i (clk_ref),
    .clk_125m_gtp_n_i (~clk_ref),
    .clk_20m_vcxo_i(clk_20m),
    // Connect the gigabit output of one SPEC with the RX input of the other,
    // and vice-versa.
    .sfp_txp_o(b_to_a_p),
    .sfp_txn_o(b_to_a_n),
    .sfp_rxp_i(a_to_b_p),
    .sfp_rxn_i(a_to_b_n),
    .dio_p_o ( dio_out_b )
    );
    assign pulse_out = dio_out_b[2];
    // observe the link LEDs on both sides, and tell us when the link is ready.
    wire link_up_a = SPEC_A.cmp_xwrc_board_spec.led_link_o;
    wire link_up_b = SPEC_B.cmp_xwrc_board_spec.led_link_o;
    initial begin
    // wait until both SPECs see the Ethernet link. Otherwise the packet we're going
    // to send might end up in void...
    $display("Start very looooong wait until link is OK (over 600us)");
    #520us
    wait(link_up_a == 1'b1 && link_up_b == 1'b1);
    #10us
    $display("Stop very looooong wait until link is OK");
    forever begin // send a pulse every 30 us;
    pulse_in = 1;
    #1us;
    pulse_in = 0;
    #30us;
    end
    end
    endmodule // main
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/run.do → testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/run.do
    View file @ bb25c738
    # make -f Makefile > /dev/null 2>&1
    # Modelsim run script
    vsim -L unisim -L secureip work.main -voptargs="+acc"
    set NumericStdNoWarnings 1
    set StdArithNoWarnings 1
    do wave.do
    do ../wave.do
    run 40000us
    wave zoomfull
    radix -hex
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/Manifest.py 0 → 100644
    View file @ bb25c738
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    sim_tool="riviera"
    top_module="main"
    vcom_opt="-relax -packagevhdlsv"
    include_dirs = [ "../" ]
    modules = {
    "local" : [ "../" ]
    }
    files = [ "main.sv" ]
    \ No newline at end of file
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv → testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/main.sv
    View file @ bb25c738
    ......@@ -35,13 +35,12 @@ module main;
    wire pulse_out;
    wire [4:0] dio_out_b;
    // This time we have two SPECs talking to each other in the same testbench
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_A (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    ......@@ -66,7 +65,8 @@ module main;
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_B (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    ......@@ -91,8 +91,8 @@ module main;
    // observe the link LEDs on both sides, and tell us when the link is ready.
    wire link_up_a = $signal_agent("SPEC_A.cmp_xwrc_board_spec.led_link_o","led_link_o",1);
    wire link_up_b = $signal_agent("SPEC_B.cmp_xwrc_board_spec.led_link_o","lend_link_o",1);
    wire link_up_a = $signal_agent("SPEC_A.cmp_xwrc_board_spec.led_link_o","link_up_a",1);
    wire link_up_b = $signal_agent("SPEC_B.cmp_xwrc_board_spec.led_link_o","link_up_b",1);
    initial begin
    // wait until both SPECs see the Ethernet link. Otherwise the packet we're going
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/run.do 0 → 100644
    View file @ bb25c738
    # Riviera run script
    vsim -L unisim -L secureip work.main +access +r +access +w_nets -ieee_nowarn
    do ../wave_ci.do
    run 40000us
    wave zoomfull
    radix -hexadecimal
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
    View file @ bb25c738
    ......@@ -33,6 +33,7 @@ add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board
    add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
    add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
    add wave -noupdate -divider {SPEC B - WR timing}
    add wave -noupdate -radix hexadecimal /main/SPEC_B/dio_p_o(2)
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave_ci.do
    View file @ bb25c738
    ......@@ -33,6 +33,7 @@ add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/p
    add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
    add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
    add wave -divider {SPEC B - WR timing}
    add wave -radix hexadecimal /main/SPEC_B/dio_p_o(2)
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
    ......
    testbench/wrc_core/Manifest.py
    View file @ bb25c738
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    #sim_tool = "modelsim"
    sim_tool = "riviera"
    top_module = "main"
    fetchto = "../../ip_cores"
    vlog_opt = "+incdir+../../sim"
    ......@@ -22,4 +14,3 @@ modules = { "local" : [ "../../",
    "../../ip_cores/gn4124-core" ]}
    testbench/wrc_core/functions.svh
    View file @ bb25c738
    ......@@ -48,14 +48,14 @@ semaphore txPkt = new(1);
    */
    task send_frames(WBPacketSource src, int n_packets, int ifg = 0 /*[us]*/);
    // TODO: improve the IFG: allow to make it tighter
    int i, seed = 0,n1=0,n2=0;
    automatic int i, seed = 0,n1=0,n2=0;
    int cur_size, dir;
    EthPacket pkt, tmpl;
    EthPacket to_ext[$], to_minic[$];
    EthPacketGenerator gen = new;
    automatic EthPacketGenerator gen = new;
    int random_ifg; //us
    int min_ifg = 1; //us
    int max_ifg = 100;//us
    automatic int min_ifg = 1; //us
    automatic int max_ifg = 100;//us
    tmpl = new;
    tmpl.src = '{'h22,'h33,'h44,'h44,'h55,'h66};
    ......
    testbench/wrc_core/main.sv
    View file @ bb25c738
    ......@@ -88,6 +88,15 @@
    `define BASE_SYSCON 'h20400
    `define BASE_MINIC 'h20000
    `define BASE_WRC_CPU_REGS 'hb00
    `define WRC_CPU_RESET 'h00
    `define WRC_CPU_UADDR 'h4
    `define WRC_CPU_UDATA 'h8
    /* the simulation sends frame_number frames with forced Inter-frame gap of 1 us
    and frame_number frames with random Inter-frame gap, between 1 and 100us */
    int frame_number = 100;
    module main;
    wire clk_ref;
    ......@@ -151,7 +160,7 @@ module main;
    wire wrc_snk_stall;
    wire wrc_snk_err;
    wire link_up;
    // globa variables for "tiemout" in case the transmitted frames are not received
    // globa variables for "timeout" in case the transmitted frames are not received
    int rx_sth = 0;
    int tx_sth = 0;
    int wait_cnt = 0;
    ......@@ -164,8 +173,8 @@ module main;
    .g_address_granularity (BYTE),
    .g_tx_runt_padding (1),
    .g_with_external_clock_input(1),
    .g_dpram_initf ("../../bin/wrpc/wrc_phy8_sim.bram"),
    .g_dpram_size (131072/4),
    .g_dpram_initf ("../../../bin/wrpc/wrc.bram"),
    .g_dpram_size (196608/4),
    .g_diag_id (1),
    .g_diag_ver (2),
    .g_diag_ro_size (5),
    ......@@ -353,7 +362,6 @@ module main;
    CSimDrv_WR_Endpoint ep_drv;
    uint64_t val;
    int frame_number = 10000;
    @(posedge rst_n);
    repeat(3) @(posedge clk_sys);
    ......@@ -381,6 +389,21 @@ module main;
    #1us;
    acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee );
    // set hdl_testbench structure used for communication with risc-v software
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_RESET, 1);
    // magic - addr = 0x4000 (in bytes), data = 0x4d433ebc
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1000);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'hbc3e434d);
    // version - addr = 0x4004 (in bytes), data = 1
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1001);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h01000000);
    // test_num - addr = 0x4008 (in bytes), data = 1
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1002);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h01000000);
    // flag - addr = 0x400C (in bytes), data = 0x12345678
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1003);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h78563412);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_RESET, 0);
    $display("");$display("");$display("");$display("");
    $display("====================================================");
    ......@@ -404,27 +427,27 @@ module main;
    tx_sth = 0; //after having received all the frames, indicate that no frames
    //are being transmitted, i.e. betweeen tx and rx
    #100us;
    $finish; //finish
    //$stop; //finish
    end
    initial begin /// receive frames from WRPC (looped back or sent by LM32), loopback frames
    /// sent from LM32
    EthPacket pkt;
    mac_addr_t PTP_MAC='{'h01,'h1b,'h19,'h00,'h00,'h00};
    mac_addr_t SELF_MAC='{'h22,'h33,'h44,'h44,'h55,'h66};
    automatic mac_addr_t PTP_MAC='{'h01,'h1b,'h19,'h00,'h00,'h00};
    automatic mac_addr_t SELF_MAC='{'h22,'h33,'h44,'h44,'h55,'h66};
    string codes [integer];
    int i = 0, correct = 0, j;
    int drop_first = 1;
    automatic int i = 0, correct = 0, j;
    automatic int drop_first = 1;
    int size_pos;
    CSimDrv_Minic minic;
    EthPacket rxp;
    int prev_size=0;
    automatic int prev_size=0;
    uint64_t val64;
    uint32_t seqID=0;
    int cnt = 0, stat = 0, ret = 0;
    int total_cnt=0;
    int self_seqID_reg=0, self_seqID_rx=0; //registered/expected and received seqID from simulation
    int lm32_seqID_reg=0, lm32_seqID_rx=0; //registered/expected and received seqID from LM32
    automatic uint32_t seqID=0;
    automatic int cnt = 0, stat = 0, ret = 0;
    automatic int total_cnt=0;
    automatic int self_seqID_reg=0, self_seqID_rx=0; //registered/expected and received seqID from simulation
    automatic int lm32_seqID_reg=0, lm32_seqID_rx=0; //registered/expected and received seqID from LM32
    codes['hAA]="Frame OK - first";
    codes['hBB]="Frame OK";
    ......@@ -485,6 +508,9 @@ module main;
    if(self_seqID_reg != self_seqID_rx)
    $warning("simulation-generated ERROR: wrong seqID");
    self_seqID_reg = self_seqID_rx +1;
    // reset self_seqID_reg when send_frames is called again
    if (self_seqID_reg == frame_number)
    self_seqID_reg = 0;
    end
    /// ///////////////////////////////////////////////////////////////////////////////////
    /// received something else, probably corrupted frame
    ......@@ -515,7 +541,7 @@ module main;
    #0.5us;
    if (wait_cnt > 2000) begin // this is too much waiting, error
    $warning("ERROR: RX TIMEOUT, no frame was received within expected timeout");
    $finish;
    $stop;
    end
    else if(rx_sth==0 & tx_sth == 1) // if transmission ongoing and nothing received, count
    wait_cnt++;
    ......
    testbench/wrc_core/modelsim/Manifest.py 0 → 100644
    View file @ bb25c738
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    top_module = "main"
    sim_tool = "modelsim"
    vcom_opt="-mixedsvvh"
    include_dirs = [ "../../../sim",
    "../" ]
    modules = {
    "local" : [ "../" ]
    }
    \ No newline at end of file
    testbench/wrc_core/run.do → testbench/wrc_core/modelsim/run.do
    View file @ bb25c738
    #vlog -dpiheader dpi/minic_dpi.h -sv main.sv +incdir+"." +incdir+../../sim
    vlog -sv main.sv +incdir+"." +incdir+../../sim
    #make -f Makefile
    #vsim -sv_lib dpi/minic -L unisim -t 10fs work.main -voptargs="+acc"
    # Modelsim run script
    # execute: vsim -c -do "run.do"
    vsim -L unisim -t 10fs work.main -voptargs="+acc"
    set StdArithNoWarnings 1
    set NumericStdNoWarnings 1
    do wave.do
    do ../wave.do
    radix -hexadecimal
    run 200ms
    wave zoomfull
    ......
    testbench/wrc_core/riviera/Manifest.py 0 → 100644
    View file @ bb25c738
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    top_module = "main"
    sim_tool = "riviera"
    vcom_opt="-relax -packagevhdlsv"
    fetchto = "../../../ip_cores"
    vlog_opt = "+incdir+../../sim"
    include_dirs = [ "../../../sim",
    "../" ]
    modules = {
    "local" : [ "../" ]
    }
    \ No newline at end of file
    testbench/wrc_core/riviera/run.do 0 → 100644
    View file @ bb25c738
    # Riviera run script
    # execute: vsim -c -do "run.do"
    vsim -L unisim -t 10fs work.main +access +r -ieee_nowarn
    do ../wave_ci.do
    radix -hexadecimal
    run 200ms
    wave zoomfull
    radix -hexadecimal
    testbench/wrc_core/wave.do
    View file @ bb25c738
    This diff is collapsed.
    top/spec_1_1/wr_streamers_demo/spec_top.vhd
    View file @ bb25c738
    ......@@ -80,7 +80,8 @@ entity spec_top is
    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    g_simulation : integer := 0
    g_simulation : integer := 0;
    g_dpram_size : integer := (144*1024/4)
    );
    port (
    ---------------------------------------------------------------------------
    ......@@ -260,7 +261,7 @@ architecture top of spec_top is
    -----------------------------------------------------------------------------
    -- Trigger-to-output value, in 8 ns ticks. Set by default to 20us to work
    -- for 10km+ fibers.
    constant c_PULSE_DELAY : integer := 30000/8;
    constant c_PULSE_DELAY : integer := 20000/8;
    constant tx_streamer_params : t_tx_streamer_params := (
    -- We send each timestamp (40 TAI bits + 28
    ......@@ -443,11 +444,12 @@ begin -- architecture top
    -- The WR PTP core board package
    -----------------------------------------------------------------------------
    cmp_xwrc_board_spec : xwrc_board_spec
    cmp_xwrc_board_spec : entity work.xwrc_board_spec
    generic map (
    g_simulation => g_simulation,
    g_with_external_clock_input => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_dpram_size => g_dpram_size,
    g_fabric_iface => STREAMERS,
    g_tx_streamer_params => tx_streamer_params,
    g_rx_streamer_params => rx_streamer_params)
    ......
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