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White Rabbit core collection
Commit 5f323f44 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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arria2 phy: remove generated files like the arria5

parent 2fd163fd
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Showing with 351 additions and 4034 deletions
platform/altera/Manifest.py
View file @ 5f323f44
def __helper():
dirs = [
"dmtd_pll",
"ref_pll",
"sys_pll",
]
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "altera_pkg.vhd" ]
modules = {"local": [ "wr_arria5_phy", "wr_gxb_phy_arria2", "dmtd_pll", "ref_pll", "sys_pll" ] }
modules = {"local": __helper() }
platform/altera/altera_pkg.vhd
View file @ 5f323f44
......@@ -32,7 +32,7 @@ package wr_altera_pkg is
);
end component;
component wr_gxb_phy_arriaii
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
......
platform/altera/wr_arria2_phy/.gitignore 0 → 100644
View file @ 5f323f44
arria2_phy.cmp
arria2_phy.ppf
arria2_phy.qip
arria2_phy.vhd
arria2_phy_reconf.cmp
arria2_phy_reconf.qip
arria2_phy_reconf.vhd
arria2_phy_reconf_inst.vhd
arria2_rxclkout.cmp
arria2_rxclkout.qip
arria2_rxclkout.vhd
platform/altera/wr_arria2_phy/Manifest.py 0 → 100644
View file @ 5f323f44
files = [
"wr_arria2_phy.vhd",
"wr_arria2_phy.qip",
];
platform/altera/wr_arria2_phy/arria2_phy.txt 0 → 100644
View file @ 5f323f44
This diff is collapsed.
platform/altera/wr_arria2_phy/arria2_phy_reconf.txt 0 → 100644
View file @ 5f323f44
-- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt2gxb_reconfig
--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 11.1 cbx_alt2gxb_reconfig 2011:10:31:21:09:45:SJ cbx_alt_cal 2011:10:31:21:09:45:SJ cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_altsyncram 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 11.1 cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "0"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
platform/altera/wr_gxb_phy_arria2/rxclkout.vhd → platform/altera/wr_arria2_phy/arria2_rxclkout.txt
View file @ 5f323f44
......@@ -3,143 +3,9 @@
-- VERSION: WM1.0
-- MODULE: altclkctrl
-- ============================================================
-- File Name: rxclkout.vhd
-- Megafunction Name(s):
-- altclkctrl
--
-- Simulation Library Files(s):
-- arriaii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 11.1SP1 cbx_altclkbuf 2011:11:23:21:11:17:SJ cbx_cycloneii 2011:11:23:21:11:17:SJ cbx_lpm_add_sub 2011:11:23:21:11:17:SJ cbx_lpm_compare 2011:11:23:21:11:17:SJ cbx_lpm_decode 2011:11:23:21:11:17:SJ cbx_lpm_mux 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_stratix 2011:11:23:21:11:17:SJ cbx_stratixii 2011:11:23:21:11:17:SJ cbx_stratixiii 2011:11:23:21:11:17:SJ cbx_stratixv 2011:11:23:21:11:17:SJ VERSION_END
LIBRARY arriaii;
USE arriaii.all;
--synthesis_resources = clkctrl 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rxclkout_altclkctrl_dfe IS
PORT
(
ena : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
outclk : OUT STD_LOGIC
);
END rxclkout_altclkctrl_dfe;
ARCHITECTURE RTL OF rxclkout_altclkctrl_dfe IS
SIGNAL wire_sd1_outclk : STD_LOGIC;
--SIGNAL clkselect : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT arriaii_clkena
GENERIC
(
clock_type : STRING;
ena_register_mode : STRING := "falling edge";
lpm_type : STRING := "arriaii_clkena"
);
PORT
(
ena : IN STD_LOGIC;
enaout : OUT STD_LOGIC;
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--clkselect <= (OTHERS => '0');
outclk <= wire_sd1_outclk;
sd1 : arriaii_clkena
GENERIC MAP (
clock_type => "Global Clock",
ena_register_mode => "falling edge"
)
PORT MAP (
ena => ena,
inclk => inclk(0),
outclk => wire_sd1_outclk
);
END RTL; --rxclkout_altclkctrl_dfe
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rxclkout IS
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
END rxclkout;
ARCHITECTURE RTL OF rxclkout IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT rxclkout_altclkctrl_dfe
PORT (
ena : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire1 <= '1';
sub_wire4_bv(2 DOWNTO 0) <= "000";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
outclk <= sub_wire0;
sub_wire2 <= inclk;
sub_wire3 <= sub_wire4(2 DOWNTO 0) & sub_wire2;
rxclkout_altclkctrl_dfe_component : rxclkout_altclkctrl_dfe
PORT MAP (
ena => sub_wire1,
inclk => sub_wire3,
outclk => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
......
platform/altera/wr_arria2_phy/wr_arria2_phy.qip 0 → 100644
View file @ 5f323f44
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy_reconf.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_rxclkout.qip"]
platform/altera/wr_arria2_phy/wr_arria2_phy.tcl 0 → 100644
View file @ 5f323f44
set files { arria2_phy arria2_phy_reconf arria2_rxclkout }
set dir [file dirname [info script]]
post_message "Testing for megawizard regeneration in $dir:$files"
foreach i $files {
if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
post_message "Regenerating $i using qmegawiz"
file copy -force "$dir/$i.txt" "$dir/$i.vhd"
set sf [open "| qmegawiz -silent $dir/$i.vhd" "r"]
while {[gets $sf line] >= 0} { post_message "$line" }
close $sf
file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
}
}
platform/altera/wr_gxb_phy_arria2/wr_gxb_phy_arriaii.vhd → platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
View file @ 5f323f44
......@@ -57,7 +57,7 @@ library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gxb_phy_arriaii is
entity wr_arria2_phy is
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
......@@ -86,17 +86,17 @@ entity wr_gxb_phy_arriaii is
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end wr_gxb_phy_arriaii;
end wr_arria2_phy;
architecture rtl of wr_gxb_phy_arriaii is
architecture rtl of wr_arria2_phy is
component rxclkout
component arria2_rxclkout
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component arria_phy
component arria2_phy
port (
cal_blk_clk : in std_logic;
pll_inclk : in std_logic;
......@@ -125,7 +125,7 @@ architecture rtl of wr_gxb_phy_arriaii is
tx_dataout : out std_logic_vector (0 downto 0));
end component;
component altgx_reconf
component arria2_phy_reconf
port (
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (16 downto 0);
......@@ -199,13 +199,13 @@ architecture rtl of wr_gxb_phy_arriaii is
begin
rx_rbclk_o <= clk_rx;
U_RxClkout : rxclkout
U_RxClkout : arria2_rxclkout
port map (
inclk => clk_rx_gxb,
outclk => clk_rx);
-- Altera PHY calibration block
U_Reconf : altgx_reconf
U_Reconf : arria2_phy_reconf
port map (
reconfig_clk => clk_reconf_i,
reconfig_fromgxb => reconfig_fromgxb,
......@@ -213,7 +213,7 @@ begin
reconfig_togxb => reconfig_togxb);
--- The serializer and byte aligner
U_The_PHY : arria_phy
U_The_PHY : arria2_phy
port map (
-- Clocks feeding the CMU and CRU of the transceiver
pll_inclk => clk_pll_i,
......
platform/altera/wr_gxb_phy_arria2/Manifest.py deleted 100644 → 0
View file @ 2fd163fd
files = [
"altgx_reconf.vhd",
"arria_phy.vhd",
"rxclkout.vhd",
"wr_gxb_phy_arriaii.vhd",
];
if (action == "simulation"):
modules = { "local" : "sim" };
platform/altera/wr_gxb_phy_arria2/altgx_reconf.vhd deleted 100644 → 0
View file @ 2fd163fd
This diff is collapsed.
platform/altera/wr_gxb_phy_arria2/arria_phy.cmp deleted 100644 → 0
View file @ 2fd163fd
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component arria_phy
PORT
(
cal_blk_clk : IN STD_LOGIC ;
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_cruclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_enapatternalign : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_seriallpbken : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_bitslipboundaryselect : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_bitslipboundaryselectout : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
platform/altera/wr_gxb_phy_arria2/arria_phy.ppf deleted 100644 → 0
View file @ 2fd163fd
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Arria II GX" variation_name="arria_phy" megafunction_name="ALTGX" specifies="all_ports">
<global>
<pin name="cal_blk_clk" direction="input" scope="external" />
<pin name="pll_inclk" direction="input" scope="external" />
<pin name="pll_powerdown[0..0]" direction="input" scope="external" />
<pin name="reconfig_clk" direction="input" scope="external" />
<pin name="reconfig_togxb[3..0]" direction="input" scope="external" />
<pin name="rx_analogreset[0..0]" direction="input" scope="external" />
<pin name="rx_cruclk[0..0]" direction="input" scope="external" />
<pin name="rx_datain[0..0]" direction="input" scope="external" />
<pin name="rx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="rx_enapatternalign[0..0]" direction="input" scope="external" />
<pin name="rx_seriallpbken[0..0]" direction="input" scope="external" />
<pin name="tx_bitslipboundaryselect[4..0]" direction="input" scope="external" />
<pin name="tx_datain[9..0]" direction="input" scope="external" />
<pin name="tx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="pll_locked[0..0]" direction="output" scope="external" />
<pin name="reconfig_fromgxb[16..0]" direction="output" scope="external" />
<pin name="rx_bitslipboundaryselectout[4..0]" direction="output" scope="external" />
<pin name="rx_clkout[0..0]" direction="output" scope="external" />
<pin name="rx_dataout[9..0]" direction="output" scope="external" />
<pin name="rx_freqlocked[0..0]" direction="output" scope="external" />
<pin name="rx_patterndetect[0..0]" direction="output" scope="external" />
<pin name="rx_pll_locked[0..0]" direction="output" scope="external" />
<pin name="rx_syncstatus[0..0]" direction="output" scope="external" />
<pin name="tx_clkout[0..0]" direction="output" scope="external" />
<pin name="tx_dataout[0..0]" direction="output" scope="external" />
</global>
</pinplan>
platform/altera/wr_gxb_phy_arria2/arria_phy.qip deleted 100644 → 0
View file @ 2fd163fd
set_global_assignment -name IP_TOOL_NAME "ALTGX"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "arria_phy.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "arria_phy.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "arria_phy.ppf"]
platform/altera/wr_gxb_phy_arria2/arria_phy.vhd deleted 100644 → 0
View file @ 2fd163fd
This source diff could not be displayed because it is too large. You can view the blob instead.
platform/altera/wr_gxb_phy_arria2/rxclkout.cmp deleted 100644 → 0
View file @ 2fd163fd
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component rxclkout
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
end component;
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