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White Rabbit core collection
Commit 5f323f44 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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arria2 phy: remove generated files like the arria5

parent 2fd163fd
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Showing with 351 additions and 4034 deletions
platform/altera/Manifest.py
View file @ 5f323f44
def __helper():
dirs = [
"dmtd_pll",
"ref_pll",
"sys_pll",
]
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "altera_pkg.vhd" ]
modules = {"local": [ "wr_arria5_phy", "wr_gxb_phy_arria2", "dmtd_pll", "ref_pll", "sys_pll" ] }
modules = {"local": __helper() }
platform/altera/altera_pkg.vhd
View file @ 5f323f44
......@@ -32,7 +32,7 @@ package wr_altera_pkg is
);
end component;
component wr_gxb_phy_arriaii
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
......
platform/altera/wr_arria2_phy/.gitignore 0 → 100644
View file @ 5f323f44
arria2_phy.cmp
arria2_phy.ppf
arria2_phy.qip
arria2_phy.vhd
arria2_phy_reconf.cmp
arria2_phy_reconf.qip
arria2_phy_reconf.vhd
arria2_phy_reconf_inst.vhd
arria2_rxclkout.cmp
arria2_rxclkout.qip
arria2_rxclkout.vhd
platform/altera/wr_arria2_phy/Manifest.py 0 → 100644
View file @ 5f323f44
files = [
"wr_arria2_phy.vhd",
"wr_arria2_phy.qip",
];
platform/altera/wr_arria2_phy/arria2_phy.txt 0 → 100644
View file @ 5f323f44
-- megafunction wizard: %ALTGX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt4gxb
--alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="5" intended_device_variant="ANY" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="iqtxrxclk" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="cpri" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="none" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=10 rx_common_mode="0.82v" rx_cru_bandwidth_type="low" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_low_latency_mode="false" rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_flip_rx_out="false" rx_force_signal_detect="true" rx_phfiforegmode="true" rx_ppmselect=9 rx_rate_match_fifo_mode="none" rx_run_length=160 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="false" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rising_edge_triggered_pattern_align="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="none" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_bitslip_enable="true" tx_channel_width=10 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_datapath_low_latency_mode="false" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_flip_tx_in="false" tx_force_disparity_mode="false" tx_phfiforegmode="true" tx_pll_bandwidth_type="medium" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_bitslipboundaryselectout rx_clkout rx_cruclk rx_datain rx_dataout rx_digitalreset rx_enapatternalign rx_freqlocked rx_patterndetect rx_pll_locked rx_seriallpbken rx_syncstatus tx_bitslipboundaryselect tx_clkout tx_datain tx_dataout tx_digitalreset
--VERSION_BEGIN 11.1SP1 cbx_alt4gxb 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_tgx 2011:11:23:21:11:17:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
-- Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
-- Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
-- Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
-- Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "62.5"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "Deterministic Latency"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 78.125 125.0 156.25 250.0 312.5 500.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "Deterministic Latency"
-- Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "X1"
-- Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
-- Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
-- Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
-- Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
-- Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "1"
-- Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
-- Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
-- Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "5"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
-- Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
-- Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "iqtxrxclk"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
-- Retrieval info: CONSTANT: PROTOCOL STRING "cpri"
-- Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
-- Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "none"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
-- Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
-- Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
-- Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "10"
-- Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
-- Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Low"
-- Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
-- Retrieval info: CONSTANT: RX_DATAPATH_LOW_LATENCY_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
-- Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
-- Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_FLIP_RX_OUT STRING "false"
-- Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
-- Retrieval info: CONSTANT: RX_PHFIFOREGMODE STRING "true"
-- Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "9"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "none"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH STRING "160"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
-- Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
-- Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
-- Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
-- Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_RISING_EDGE_TRIGGERED_PATTERN_ALIGN STRING "false"
-- Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "none"
-- Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
-- Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "10"
-- Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
-- Retrieval info: CONSTANT: TX_DATAPATH_LOW_LATENCY_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
-- Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_FLIP_TX_IN STRING "false"
-- Retrieval info: CONSTANT: TX_FORCE_DISPARITY_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_PHFIFOREGMODE STRING "true"
-- Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Medium"
-- Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
-- Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
-- Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
-- Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
-- Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
-- Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
-- Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
-- Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
-- Retrieval info: CONSTANT: reconfig_calibration STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
-- Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
-- Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5"
-- Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
-- Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4"
-- Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
-- Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
-- Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
-- Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
-- Retrieval info: CONSTANT: tx_bitslip_enable STRING "true"
-- Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
-- Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5"
-- Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
-- Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4"
-- Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
-- Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
-- Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
-- Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
-- Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
-- Retrieval info: USED_PORT: rx_bitslipboundaryselectout 0 0 5 0 OUTPUT NODEFVAL "rx_bitslipboundaryselectout[4..0]"
-- Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
-- Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
-- Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
-- Retrieval info: USED_PORT: rx_dataout 0 0 10 0 OUTPUT NODEFVAL "rx_dataout[9..0]"
-- Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
-- Retrieval info: USED_PORT: rx_enapatternalign 0 0 1 0 INPUT NODEFVAL "rx_enapatternalign[0..0]"
-- Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
-- Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
-- Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
-- Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
-- Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
-- Retrieval info: USED_PORT: tx_bitslipboundaryselect 0 0 5 0 INPUT NODEFVAL "tx_bitslipboundaryselect[4..0]"
-- Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
-- Retrieval info: USED_PORT: tx_datain 0 0 10 0 INPUT NODEFVAL "tx_datain[9..0]"
-- Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
-- Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
-- Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
-- Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
-- Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
-- Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
-- Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_enapatternalign 0 0 1 0 rx_enapatternalign 0 0 1 0
-- Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
-- Retrieval info: CONNECT: @tx_bitslipboundaryselect 0 0 5 0 tx_bitslipboundaryselect 0 0 5 0
-- Retrieval info: CONNECT: @tx_datain 0 0 10 0 tx_datain 0 0 10 0
-- Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
-- Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: rx_bitslipboundaryselectout 0 0 5 0 @rx_bitslipboundaryselectout 0 0 5 0
-- Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
-- Retrieval info: CONNECT: rx_dataout 0 0 10 0 @rx_dataout 0 0 10 0
-- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
-- Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
-- Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
-- Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
-- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii_hssi
-- Retrieval info: CBX_MODULE_PREFIX: ON
platform/altera/wr_arria2_phy/arria2_phy_reconf.txt 0 → 100644
View file @ 5f323f44
-- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt2gxb_reconfig
--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 11.1 cbx_alt2gxb_reconfig 2011:10:31:21:09:45:SJ cbx_alt_cal 2011:10:31:21:09:45:SJ cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_altsyncram 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 11.1 cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "0"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
platform/altera/wr_gxb_phy_arria2/rxclkout.vhd → platform/altera/wr_arria2_phy/arria2_rxclkout.txt
View file @ 5f323f44
......@@ -3,143 +3,9 @@
-- VERSION: WM1.0
-- MODULE: altclkctrl
-- ============================================================
-- File Name: rxclkout.vhd
-- Megafunction Name(s):
-- altclkctrl
--
-- Simulation Library Files(s):
-- arriaii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 11.1SP1 cbx_altclkbuf 2011:11:23:21:11:17:SJ cbx_cycloneii 2011:11:23:21:11:17:SJ cbx_lpm_add_sub 2011:11:23:21:11:17:SJ cbx_lpm_compare 2011:11:23:21:11:17:SJ cbx_lpm_decode 2011:11:23:21:11:17:SJ cbx_lpm_mux 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_stratix 2011:11:23:21:11:17:SJ cbx_stratixii 2011:11:23:21:11:17:SJ cbx_stratixiii 2011:11:23:21:11:17:SJ cbx_stratixv 2011:11:23:21:11:17:SJ VERSION_END
LIBRARY arriaii;
USE arriaii.all;
--synthesis_resources = clkctrl 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rxclkout_altclkctrl_dfe IS
PORT
(
ena : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
outclk : OUT STD_LOGIC
);
END rxclkout_altclkctrl_dfe;
ARCHITECTURE RTL OF rxclkout_altclkctrl_dfe IS
SIGNAL wire_sd1_outclk : STD_LOGIC;
--SIGNAL clkselect : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT arriaii_clkena
GENERIC
(
clock_type : STRING;
ena_register_mode : STRING := "falling edge";
lpm_type : STRING := "arriaii_clkena"
);
PORT
(
ena : IN STD_LOGIC;
enaout : OUT STD_LOGIC;
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--clkselect <= (OTHERS => '0');
outclk <= wire_sd1_outclk;
sd1 : arriaii_clkena
GENERIC MAP (
clock_type => "Global Clock",
ena_register_mode => "falling edge"
)
PORT MAP (
ena => ena,
inclk => inclk(0),
outclk => wire_sd1_outclk
);
END RTL; --rxclkout_altclkctrl_dfe
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rxclkout IS
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
END rxclkout;
ARCHITECTURE RTL OF rxclkout IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT rxclkout_altclkctrl_dfe
PORT (
ena : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire1 <= '1';
sub_wire4_bv(2 DOWNTO 0) <= "000";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
outclk <= sub_wire0;
sub_wire2 <= inclk;
sub_wire3 <= sub_wire4(2 DOWNTO 0) & sub_wire2;
rxclkout_altclkctrl_dfe_component : rxclkout_altclkctrl_dfe
PORT MAP (
ena => sub_wire1,
inclk => sub_wire3,
outclk => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
......
platform/altera/wr_arria2_phy/wr_arria2_phy.qip 0 → 100644
View file @ 5f323f44
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy_reconf.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_rxclkout.qip"]
platform/altera/wr_arria2_phy/wr_arria2_phy.tcl 0 → 100644
View file @ 5f323f44
set files { arria2_phy arria2_phy_reconf arria2_rxclkout }
set dir [file dirname [info script]]
post_message "Testing for megawizard regeneration in $dir:$files"
foreach i $files {
if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
post_message "Regenerating $i using qmegawiz"
file copy -force "$dir/$i.txt" "$dir/$i.vhd"
set sf [open "| qmegawiz -silent $dir/$i.vhd" "r"]
while {[gets $sf line] >= 0} { post_message "$line" }
close $sf
file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
}
}
platform/altera/wr_gxb_phy_arria2/wr_gxb_phy_arriaii.vhd → platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
View file @ 5f323f44
......@@ -57,7 +57,7 @@ library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gxb_phy_arriaii is
entity wr_arria2_phy is
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
......@@ -86,17 +86,17 @@ entity wr_gxb_phy_arriaii is
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end wr_gxb_phy_arriaii;
end wr_arria2_phy;
architecture rtl of wr_gxb_phy_arriaii is
architecture rtl of wr_arria2_phy is
component rxclkout
component arria2_rxclkout
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component arria_phy
component arria2_phy
port (
cal_blk_clk : in std_logic;
pll_inclk : in std_logic;
......@@ -125,7 +125,7 @@ architecture rtl of wr_gxb_phy_arriaii is
tx_dataout : out std_logic_vector (0 downto 0));
end component;
component altgx_reconf
component arria2_phy_reconf
port (
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (16 downto 0);
......@@ -199,13 +199,13 @@ architecture rtl of wr_gxb_phy_arriaii is
begin
rx_rbclk_o <= clk_rx;
U_RxClkout : rxclkout
U_RxClkout : arria2_rxclkout
port map (
inclk => clk_rx_gxb,
outclk => clk_rx);
-- Altera PHY calibration block
U_Reconf : altgx_reconf
U_Reconf : arria2_phy_reconf
port map (
reconfig_clk => clk_reconf_i,
reconfig_fromgxb => reconfig_fromgxb,
......@@ -213,7 +213,7 @@ begin
reconfig_togxb => reconfig_togxb);
--- The serializer and byte aligner
U_The_PHY : arria_phy
U_The_PHY : arria2_phy
port map (
-- Clocks feeding the CMU and CRU of the transceiver
pll_inclk => clk_pll_i,
......
platform/altera/wr_gxb_phy_arria2/Manifest.py deleted 100644 → 0
View file @ 2fd163fd
files = [
"altgx_reconf.vhd",
"arria_phy.vhd",
"rxclkout.vhd",
"wr_gxb_phy_arriaii.vhd",
];
if (action == "simulation"):
modules = { "local" : "sim" };
platform/altera/wr_gxb_phy_arria2/altgx_reconf.vhd deleted 100644 → 0
View file @ 2fd163fd
-- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt2gxb_reconfig
-- ============================================================
-- File Name: altgx_reconf.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
-- Simulation Library Files(s):
-- altera_mf;lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 11.1 cbx_alt2gxb_reconfig 2011:10:31:21:09:45:SJ cbx_alt_cal 2011:10:31:21:09:45:SJ cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_altsyncram 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 11.1 cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altgx_reconf_alt_dprio_kuj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END altgx_reconf_alt_dprio_kuj;
ARCHITECTURE RTL OF altgx_reconf_alt_dprio_kuj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
SIGNAL wire_addr_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_addr_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL addr_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_addr_shift_reg_w_q_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL in_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_rd_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL rd_out_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_w_q_range392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_d : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL startup_cntr : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_startup_cntr_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range457w460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range461w467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range461w470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range453w454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range453w469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range453w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range461w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_mc_reg : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_state_mc_reg_w_q_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wr_out_data_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_wr_out_data_shift_reg_w_q_range327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb214w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb214w326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_agb214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_aeb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_agb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_rd_data_output_cmpr_ageb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_alb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_cmpr_aeb : STD_LOGIC;
SIGNAL wire_state_mc_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_counter_cnt_en : STD_LOGIC;
SIGNAL wire_dprio_w_lg_write_state36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_counter_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_decode_eq : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_dprioin_mux_dataout : STD_LOGIC;
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s0_to_053w54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s1_to_072w73w74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s2_to_088w89w90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wr_addr_state213w217w218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rd_data_output_state393w394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_data_state328w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s0_to_053w54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s1_to_072w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s2_to_088w89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren42w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren42w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren42w60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_addr_state213w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rd_data_output_state393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_data_state328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_072w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_done447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_idle448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren_data64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden449w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_addr_state213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL busy_state : STD_LOGIC;
SIGNAL idle_state : STD_LOGIC;
SIGNAL rd_addr_done : STD_LOGIC;
SIGNAL rd_addr_state : STD_LOGIC;
SIGNAL rd_data_done : STD_LOGIC;
SIGNAL rd_data_input_state : STD_LOGIC;
SIGNAL rd_data_output_state : STD_LOGIC;
SIGNAL rd_data_state : STD_LOGIC;
SIGNAL rdinc : STD_LOGIC;
SIGNAL read_state : STD_LOGIC;
SIGNAL s0_to_0 : STD_LOGIC;
SIGNAL s0_to_1 : STD_LOGIC;
SIGNAL s1_to_0 : STD_LOGIC;
SIGNAL s1_to_1 : STD_LOGIC;
SIGNAL s2_to_0 : STD_LOGIC;
SIGNAL s2_to_1 : STD_LOGIC;
SIGNAL startup_done : STD_LOGIC;
SIGNAL startup_idle : STD_LOGIC;
SIGNAL wr_addr_done : STD_LOGIC;
SIGNAL wr_addr_state : STD_LOGIC;
SIGNAL wr_data_done : STD_LOGIC;
SIGNAL wr_data_state : STD_LOGIC;
SIGNAL write_state : STD_LOGIC;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT lpm_decode
GENERIC
(
LPM_DECODES : NATURAL;
LPM_PIPELINE : NATURAL := 0;
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_decode"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
enable : IN STD_LOGIC := '1';
eq : OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_dprio_w_lg_w_lg_w_lg_s0_to_053w54w55w(0) <= wire_dprio_w_lg_w_lg_s0_to_053w54w(0) AND wire_state_mc_reg_w_q_range51w(0);
wire_dprio_w_lg_w_lg_w_lg_s1_to_072w73w74w(0) <= wire_dprio_w_lg_w_lg_s1_to_072w73w(0) AND wire_state_mc_reg_w_q_range70w(0);
wire_dprio_w_lg_w_lg_w_lg_s2_to_088w89w90w(0) <= wire_dprio_w_lg_w_lg_s2_to_088w89w(0) AND wire_state_mc_reg_w_q_range86w(0);
wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w(0) <= wire_dprio_w_lg_w_lg_wren42w65w(0) AND wire_dprio_w_lg_rdinc77w(0);
wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w(0) <= wire_dprio_w_lg_w_lg_wren42w65w(0) AND rden;
wire_dprio_w_lg_w_lg_w_lg_wr_addr_state213w217w218w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state213w217w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_rd_data_output_state393w394w(0) <= wire_dprio_w_lg_rd_data_output_state393w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_wr_data_state328w329w(0) <= wire_dprio_w_lg_wr_data_state328w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_s0_to_053w54w(0) <= wire_dprio_w_lg_s0_to_053w(0) AND wire_dprio_w_lg_s0_to_152w(0);
wire_dprio_w_lg_w_lg_s1_to_072w73w(0) <= wire_dprio_w_lg_s1_to_072w(0) AND wire_dprio_w_lg_s1_to_171w(0);
wire_dprio_w_lg_w_lg_s2_to_088w89w(0) <= wire_dprio_w_lg_s2_to_088w(0) AND wire_dprio_w_lg_s2_to_187w(0);
wire_dprio_w_lg_w_lg_wren42w65w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_wren_data64w(0);
wire_dprio_w_lg_w_lg_wren42w43w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_w_lg_rden40w41w(0);
wire_dprio_w_lg_w_lg_wren42w60w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_rdinc59w(0);
wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w(0) AND wire_dprio_w_lg_startup_done447w(0);
wire_dprio_w_lg_w_lg_wr_addr_state213w217w(0) <= wire_dprio_w_lg_wr_addr_state213w(0) AND wire_addr_shift_reg_w_q_range216w(0);
wire_dprio_w_lg_idle_state79w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w(0);
wire_dprio_w_lg_idle_state61w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren42w60w(0);
wire_dprio_w_lg_idle_state68w(0) <= idle_state AND wire_dprio_w_lg_wren67w(0);
wire_dprio_w_lg_idle_state45w(0) <= idle_state AND wire_dprio_w_lg_wren44w(0);
wire_dprio_w_lg_idle_state82w(0) <= idle_state AND wire_dprio_w_lg_wren81w(0);
wire_dprio_w_lg_rd_data_output_state393w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range392w(0);
wire_dprio_w_lg_wr_data_state328w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range327w(0);
wire_dprio_w_lg_s0_to_053w(0) <= NOT s0_to_0;
wire_dprio_w_lg_s0_to_152w(0) <= NOT s0_to_1;
wire_dprio_w_lg_s1_to_072w(0) <= NOT s1_to_0;
wire_dprio_w_lg_s1_to_171w(0) <= NOT s1_to_1;
wire_dprio_w_lg_s2_to_088w(0) <= NOT s2_to_0;
wire_dprio_w_lg_s2_to_187w(0) <= NOT s2_to_1;
wire_dprio_w_lg_startup_done447w(0) <= NOT startup_done;
wire_dprio_w_lg_startup_idle448w(0) <= NOT startup_idle;
wire_dprio_w_lg_wren42w(0) <= NOT wren;
wire_dprio_w_lg_wren_data64w(0) <= NOT wren_data;
wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w(0) <= wire_dprio_w_lg_w_lg_rden449w450w(0) OR wire_dprio_w_lg_startup_idle448w(0);
wire_dprio_w_lg_w_lg_rden40w41w(0) <= wire_dprio_w_lg_rden40w(0) OR wren_data;
wire_dprio_w_lg_w_lg_rden449w450w(0) <= wire_dprio_w_lg_rden449w(0) OR rdinc;
wire_dprio_w_lg_rden40w(0) <= rden OR rdinc;
wire_dprio_w_lg_rden449w(0) <= rden OR wren;
wire_dprio_w_lg_rdinc77w(0) <= rdinc OR rden;
wire_dprio_w_lg_rdinc59w(0) <= rdinc OR wren_data;
wire_dprio_w_lg_s0_to_156w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_053w54w55w(0);
wire_dprio_w_lg_s1_to_175w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_072w73w74w(0);
wire_dprio_w_lg_s2_to_191w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_088w89w90w(0);
wire_dprio_w_lg_wr_addr_state213w(0) <= wr_addr_state OR rd_addr_state;
wire_dprio_w_lg_wren67w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w(0);
wire_dprio_w_lg_wren44w(0) <= wren OR wire_dprio_w_lg_w_lg_wren42w43w(0);
wire_dprio_w_lg_wren81w(0) <= wren OR wren_data;
busy <= busy_state;
busy_state <= (write_state OR read_state);
dataout <= in_data_shift_reg;
dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range461w470w(0));
dprioin <= wire_dprioin_mux_dataout;
dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range453w458w(0) AND (NOT startup_cntr(2))));
idle_state <= wire_state_mc_decode_eq(0);
rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
rdinc <= '0';
read_state <= (rd_addr_state OR rd_data_state);
s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
s0_to_1 <= ((wire_dprio_w_lg_idle_state45w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state68w(0));
s1_to_1 <= ((wire_dprio_w_lg_idle_state61w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state82w(0));
s2_to_1 <= (wire_dprio_w_lg_idle_state79w(0) OR (rd_addr_state AND rd_addr_done));
startup_done <= (wire_startup_cntr_w_lg_w_q_range461w467w(0) AND startup_cntr(1));
startup_idle <= (wire_startup_cntr_w_lg_w_q_range453w454w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
write_state <= (wr_addr_state OR wr_data_state);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
wire_addr_shift_reg_w_q_range216w(0) <= addr_shift_reg(31);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
wire_rd_out_data_shift_reg_w_q_range392w(0) <= rd_out_data_shift_reg(15);
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(0) = '1') THEN
IF (reset = '1') THEN startup_cntr(0) <= '0';
ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(1) = '1') THEN
IF (reset = '1') THEN startup_cntr(1) <= '0';
ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(2) = '1') THEN
IF (reset = '1') THEN startup_cntr(2) <= '0';
ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
END IF;
END IF;
END IF;
END PROCESS;
wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range461w462w & wire_startup_cntr_w_lg_w_q_range453w458w & wire_startup_cntr_w_lg_w_q_range453w454w);
loop0 : FOR i IN 0 TO 2 GENERATE
wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w(0);
END GENERATE loop0;
wire_startup_cntr_w_lg_w_q_range457w460w(0) <= wire_startup_cntr_w_q_range457w(0) AND wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range461w467w(0) <= wire_startup_cntr_w_q_range461w(0) AND wire_startup_cntr_w_lg_w_q_range453w454w(0);
wire_startup_cntr_w_lg_w_q_range461w470w(0) <= wire_startup_cntr_w_q_range461w(0) AND wire_startup_cntr_w_lg_w_q_range453w469w(0);
wire_startup_cntr_w_lg_w_q_range453w454w(0) <= NOT wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range453w469w(0) <= wire_startup_cntr_w_q_range453w(0) OR wire_startup_cntr_w_q_range457w(0);
wire_startup_cntr_w_lg_w_q_range453w458w(0) <= wire_startup_cntr_w_q_range453w(0) XOR wire_startup_cntr_w_q_range457w(0);
wire_startup_cntr_w_lg_w_q_range461w462w(0) <= wire_startup_cntr_w_q_range461w(0) XOR wire_startup_cntr_w_lg_w_q_range457w460w(0);
wire_startup_cntr_w_q_range453w(0) <= startup_cntr(0);
wire_startup_cntr_w_q_range457w(0) <= startup_cntr(1);
wire_startup_cntr_w_q_range461w(0) <= startup_cntr(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_191w & wire_dprio_w_lg_s1_to_175w & wire_dprio_w_lg_s0_to_156w);
END IF;
END PROCESS;
wire_state_mc_reg_w_q_range51w(0) <= state_mc_reg(0);
wire_state_mc_reg_w_q_range70w(0) <= state_mc_reg(1);
wire_state_mc_reg_w_q_range86w(0) <= state_mc_reg(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
wire_wr_out_data_shift_reg_w_q_range327w(0) <= wr_out_data_shift_reg(31);
wire_pre_amble_cmpr_w_lg_w_lg_agb214w391w(0) <= wire_pre_amble_cmpr_w_lg_agb214w(0) AND rd_data_output_state;
wire_pre_amble_cmpr_w_lg_w_lg_agb214w326w(0) <= wire_pre_amble_cmpr_w_lg_agb214w(0) AND wr_data_state;
wire_pre_amble_cmpr_w_lg_agb214w(0) <= NOT wire_pre_amble_cmpr_agb;
wire_pre_amble_cmpr_datab <= "011111";
pre_amble_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_pre_amble_cmpr_aeb,
agb => wire_pre_amble_cmpr_agb,
dataa => wire_state_mc_counter_q,
datab => wire_pre_amble_cmpr_datab
);
wire_rd_data_output_cmpr_datab <= "110000";
rd_data_output_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
ageb => wire_rd_data_output_cmpr_ageb,
alb => wire_rd_data_output_cmpr_alb,
dataa => wire_state_mc_counter_q,
datab => wire_rd_data_output_cmpr_datab
);
wire_state_mc_cmpr_datab <= (OTHERS => '1');
state_mc_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_state_mc_cmpr_aeb,
dataa => wire_state_mc_counter_q,
datab => wire_state_mc_cmpr_datab
);
wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state36w(0);
wire_dprio_w_lg_write_state36w(0) <= write_state OR read_state;
state_mc_counter : lpm_counter
GENERIC MAP (
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
clock => dpclk,
cnt_en => wire_state_mc_counter_cnt_en,
q => wire_state_mc_counter_q,
sclr => reset
);
state_mc_decode : lpm_decode
GENERIC MAP (
LPM_DECODES => 8,
LPM_WIDTH => 3
)
PORT MAP (
data => state_mc_reg,
eq => wire_state_mc_decode_eq
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state213w217w218w(0) OR (wire_pre_amble_cmpr_w_lg_agb214w(0) AND wire_dprio_w_lg_wr_addr_state213w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state328w329w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb214w326w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state393w394w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb214w391w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
END RTL; --altgx_reconf_alt_dprio_kuj
LIBRARY altera_mf;
USE altera_mf.all;
--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altgx_reconf_alt2gxb_reconfig_sfm IS
PORT
(
busy : OUT STD_LOGIC;
reconfig_clk : IN STD_LOGIC;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END altgx_reconf_alt2gxb_reconfig_sfm;
ARCHITECTURE RTL OF altgx_reconf_alt2gxb_reconfig_sfm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
SIGNAL wire_calibration_w_lg_busy12w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_w_lg_busy11w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_busy : STD_LOGIC;
SIGNAL wire_calibration_dprio_addr : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_quad_addr : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_calibration_reset : STD_LOGIC;
SIGNAL wire_w_lg_offset_cancellation_reset9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_calibration_retain_addr : STD_LOGIC;
SIGNAL wire_dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_busy : STD_LOGIC;
SIGNAL wire_dprio_datain : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dpriodisable : STD_LOGIC;
SIGNAL wire_dprio_dprioin : STD_LOGIC;
SIGNAL wire_dprio_dprioload : STD_LOGIC;
SIGNAL wire_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_w_lg_busy13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_w_lg_busy14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL address_pres_reg : STD_LOGIC_VECTOR(11 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
SIGNAL cal_busy : STD_LOGIC;
SIGNAL cal_dprioout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cal_testbuses : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL channel_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL is_adce_all_control : STD_LOGIC;
SIGNAL is_adce_continuous_single_control : STD_LOGIC;
SIGNAL is_adce_one_time_single_control : STD_LOGIC;
SIGNAL is_adce_single_control : STD_LOGIC;
SIGNAL is_adce_standby_single_control : STD_LOGIC;
SIGNAL offset_cancellation_reset : STD_LOGIC;
SIGNAL quad_address : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL reconfig_reset_all : STD_LOGIC;
SIGNAL start : STD_LOGIC;
SIGNAL transceiver_init : STD_LOGIC;
COMPONENT alt_cal
GENERIC
(
CHANNEL_ADDRESS_WIDTH : NATURAL := 1;
NUMBER_OF_CHANNELS : NATURAL;
SIM_MODEL_MODE : STRING := "FALSE";
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "alt_cal"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC;
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
COMPONENT altgx_reconf_alt_dprio_kuj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
busy <= cal_busy;
cal_busy <= wire_calibration_busy;
cal_dprioout_wire(0) <= ( reconfig_fromgxb(0));
cal_testbuses <= ( reconfig_fromgxb(4 DOWNTO 1));
channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
offset_cancellation_reset <= '0';
quad_address <= wire_calibration_quad_addr;
reconfig_reset_all <= '0';
reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
start <= '0';
transceiver_init <= '0';
loop1 : FOR i IN 0 TO 15 GENERATE
wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 15 GENERATE
wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
END GENERATE loop2;
wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
calibration : alt_cal
GENERIC MAP (
CHANNEL_ADDRESS_WIDTH => 0,
NUMBER_OF_CHANNELS => 1,
SIM_MODEL_MODE => "FALSE"
)
PORT MAP (
busy => wire_calibration_busy,
clock => reconfig_clk,
dprio_addr => wire_calibration_dprio_addr,
dprio_busy => wire_dprio_busy,
dprio_datain => wire_dprio_dataout,
dprio_dataout => wire_calibration_dprio_dataout,
dprio_rden => wire_calibration_dprio_rden,
dprio_wren => wire_calibration_dprio_wren,
quad_addr => wire_calibration_quad_addr,
remap_addr => address_pres_reg,
reset => wire_calibration_reset,
retain_addr => wire_calibration_retain_addr,
start => start,
testbuses => cal_testbuses,
transceiver_init => transceiver_init
);
wire_dprio_address <= wire_calibration_w_lg_busy12w;
wire_dprio_datain <= wire_calibration_w_lg_busy11w;
wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
dprio : altgx_reconf_alt_dprio_kuj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
datain => wire_dprio_datain,
dataout => wire_dprio_dataout,
dpclk => reconfig_clk,
dpriodisable => wire_dprio_dpriodisable,
dprioin => wire_dprio_dprioin,
dprioload => wire_dprio_dprioload,
dprioout => cal_dprioout_wire(0),
quad_address => address_pres_reg(11 DOWNTO 3),
rden => wire_dprio_rden,
reset => reconfig_reset_all,
wren => wire_dprio_wren,
wren_data => wire_calibration_retain_addr
);
PROCESS (reconfig_clk, reconfig_reset_all)
BEGIN
IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
END RTL; --altgx_reconf_alt2gxb_reconfig_sfm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altgx_reconf IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END altgx_reconf;
ARCHITECTURE RTL OF altgx_reconf IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Arria II GX;number_of_channels=1;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=17;reconfig_togxb_width=4;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altgx_reconf_alt2gxb_reconfig_sfm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
altgx_reconf_alt2gxb_reconfig_sfm_component : altgx_reconf_alt2gxb_reconfig_sfm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
busy => sub_wire0,
reconfig_togxb => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "0"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
platform/altera/wr_gxb_phy_arria2/arria_phy.cmp deleted 100644 → 0
View file @ 2fd163fd
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component arria_phy
PORT
(
cal_blk_clk : IN STD_LOGIC ;
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_cruclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_enapatternalign : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_seriallpbken : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_bitslipboundaryselect : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_bitslipboundaryselectout : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
platform/altera/wr_gxb_phy_arria2/arria_phy.ppf deleted 100644 → 0
View file @ 2fd163fd
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Arria II GX" variation_name="arria_phy" megafunction_name="ALTGX" specifies="all_ports">
<global>
<pin name="cal_blk_clk" direction="input" scope="external" />
<pin name="pll_inclk" direction="input" scope="external" />
<pin name="pll_powerdown[0..0]" direction="input" scope="external" />
<pin name="reconfig_clk" direction="input" scope="external" />
<pin name="reconfig_togxb[3..0]" direction="input" scope="external" />
<pin name="rx_analogreset[0..0]" direction="input" scope="external" />
<pin name="rx_cruclk[0..0]" direction="input" scope="external" />
<pin name="rx_datain[0..0]" direction="input" scope="external" />
<pin name="rx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="rx_enapatternalign[0..0]" direction="input" scope="external" />
<pin name="rx_seriallpbken[0..0]" direction="input" scope="external" />
<pin name="tx_bitslipboundaryselect[4..0]" direction="input" scope="external" />
<pin name="tx_datain[9..0]" direction="input" scope="external" />
<pin name="tx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="pll_locked[0..0]" direction="output" scope="external" />
<pin name="reconfig_fromgxb[16..0]" direction="output" scope="external" />
<pin name="rx_bitslipboundaryselectout[4..0]" direction="output" scope="external" />
<pin name="rx_clkout[0..0]" direction="output" scope="external" />
<pin name="rx_dataout[9..0]" direction="output" scope="external" />
<pin name="rx_freqlocked[0..0]" direction="output" scope="external" />
<pin name="rx_patterndetect[0..0]" direction="output" scope="external" />
<pin name="rx_pll_locked[0..0]" direction="output" scope="external" />
<pin name="rx_syncstatus[0..0]" direction="output" scope="external" />
<pin name="tx_clkout[0..0]" direction="output" scope="external" />
<pin name="tx_dataout[0..0]" direction="output" scope="external" />
</global>
</pinplan>
platform/altera/wr_gxb_phy_arria2/arria_phy.qip deleted 100644 → 0
View file @ 2fd163fd
set_global_assignment -name IP_TOOL_NAME "ALTGX"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "arria_phy.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "arria_phy.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "arria_phy.ppf"]
platform/altera/wr_gxb_phy_arria2/arria_phy.vhd deleted 100644 → 0
View file @ 2fd163fd
This source diff could not be displayed because it is too large. You can view the blob instead.
platform/altera/wr_gxb_phy_arria2/rxclkout.cmp deleted 100644 → 0
View file @ 2fd163fd
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component rxclkout
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
end component;
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