Previously on Altera, there was a non-deterministic delay between
transmission from clk_ref to clk_tx. This came from a FIFO in the
GXB and also that clk_tx was not compensated against clk_ref.

Using deterministic mode with PFD feedback achieves determinism.
There is only a single register instead of the FIFO and the parallel
TX clock is phase matched to the CMU reference clock.

Unfortunately, deterministic mode does not have access to force_dispval.
This necessitates using an 8b10b in the FPGA fabric.

Another change is that the CDR clock is trained by a GXB reference
clock pin for better jitter performance. It is forbidden to cascade
two PLLs in low bandwidth mode. This way the recovered clock can use
low bandwidth as it is never derived from clk_ref (also low bandwidth).

Another change is the reset logic has been rewired. Before the WRC
could reset the GXB and thus kill the RX clock. This led to bad
undefined states in the RX state machiens. Now reset as in the manual.