Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

Fixed by adding missing "else statement" in CRC_WORD state. In this
statement the dvalid is set LOW and no ('X') data is set. Without
this, the input data remainded 0xCAFE and the input dvalid remainded
HIGH, thus the escape_inserter was forcing dreq=LOW in order to
stop the input data for one cycle and insert special character.

compiled from commit:
a9add108 Merge branch 'adam-lldp-rebased' into proposed_master

Compiled from wrpc-sw commit:
c0e116b: simpler sdbfs creation by using parameters provided by Syscon HDL module

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

The streamer has a new start-up delay counter. this delay needs to be
shorter for simulation. the fact that we are running simulation was not
passed to the Tx streamer, now it is passed.

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

by default, the bram content for synthesis is specified. it is only
overriden by simulation. In this way, if the top can be both, simulated
and synthesized.

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

The binary did not work. I do not know why. I just recompiled wrpc-sw
with wrpc_sim_defconfig configuration and it works.