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Commit 6a425a6f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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svec_ref_design: update vme64x core to the latest one by Tristan

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vme64x-core @ 458475d5
Subproject commit 6994f35bdbe717f3df69e7226ee35d507ea87f5f
Subproject commit 458475d5d0dcd32c83f20a60f3efb7797341fd6c
top/svec_ref_design/svec_wr_ref_top.ucf
+ 14
− 14
View file @ 6a425a6f
......@@ -23,13 +23,13 @@ NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[7]" LOC = R7;
NET "vme_irq_n_o[6]" LOC = AH2;
NET "vme_irq_n_o[5]" LOC = AF2;
NET "vme_irq_n_o[4]" LOC = N9;
NET "vme_irq_n_o[3]" LOC = N10;
NET "vme_irq_n_o[2]" LOC = AH4;
NET "vme_irq_n_o[1]" LOC = AG4;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
......@@ -123,13 +123,13 @@ NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
......
top/svec_ref_design/svec_wr_ref_top.vhd
+ 58
− 33
View file @ 6a425a6f
......@@ -53,7 +53,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
......@@ -107,7 +107,7 @@ entity svec_wr_ref_top is
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_n_o : out std_logic_vector(7 downto 1);
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
......@@ -233,6 +233,7 @@ architecture top of svec_wr_ref_top is
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- clock and reset
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
......@@ -252,6 +253,9 @@ architecture top of svec_wr_ref_top is
signal Vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_wb_out : t_wishbone_master_out;
-- SFP
signal sfp_sda_in : std_logic;
......@@ -273,6 +277,11 @@ architecture top of svec_wr_ref_top is
begin -- architecture top
-----------------------------------------------------------------------------
-- System reset
-----------------------------------------------------------------------------
areset_n <= vme_sysreset_n_i and rst_n_i;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
......@@ -298,39 +307,56 @@ begin -- architecture top
-----------------------------------------------------------------------------
cmp_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => True,
g_USER_CSR_EXT => False,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
VME_AS_n_i => vme_as_n_i,
VME_RST_n_i => '1', -- vme_sysreset_n_i already in rst_sys_62m5_n
VME_WRITE_n_i => vme_write_n_i,
VME_AM_i => vme_am_i,
VME_DS_n_i => vme_ds_n_i,
VME_GA_i => vme_ga,
VME_BERR_o => vme_berr_o,
VME_DTACK_n_o => vme_dtack_n_o,
VME_RETRY_n_o => vme_retry_n_o,
VME_RETRY_OE_o => vme_retry_oe_o,
VME_LWORD_n_b_i => vme_lword_n_b,
VME_LWORD_n_b_o => vme_lword_n_b_out,
VME_ADDR_b_i => vme_addr_b,
VME_DATA_b_o => vme_data_b_out,
VME_ADDR_b_o => vme_addr_b_out,
VME_DATA_b_i => vme_data_b,
VME_IRQ_n_o => vme_irq_n_o,
VME_IACK_n_i => vme_iack_n_i,
VME_IACKIN_n_i => vme_iackin_n_i,
VME_IACKOUT_n_o => vme_iackout_n_o,
VME_DTACK_OE_o => vme_dtack_oe_o,
VME_DATA_DIR_o => vme_data_dir_int,
VME_DATA_OE_N_o => vme_data_oe_n_o,
VME_ADDR_DIR_o => vme_addr_dir_int,
VME_ADDR_OE_N_o => vme_addr_oe_n_o,
master_o => cnx_master_out(c_WB_MASTER_VME),
master_i => cnx_master_in(c_WB_MASTER_VME),
irq_i => '0');
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => vme_wb_out,
wb_i => cnx_master_in(c_WB_MASTER_VME));
-- Shift WB address for byte addressing
cnx_master_out(c_WB_MASTER_VME).cyc <= vme_wb_out.cyc;
cnx_master_out(c_WB_MASTER_VME).stb <= vme_wb_out.stb;
cnx_master_out(c_WB_MASTER_VME).adr <= vme_wb_out.adr(29 downto 0) & "00";
cnx_master_out(c_WB_MASTER_VME).sel <= vme_wb_out.sel;
cnx_master_out(c_WB_MASTER_VME).we <= vme_wb_out.we;
cnx_master_out(c_WB_MASTER_VME).dat <= vme_wb_out.dat;
--
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
......@@ -357,8 +383,7 @@ begin -- architecture top
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
areset_n_i => rst_n_i,
areset_edge_n_i => vme_sysreset_n_i,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
......
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