- Dec 08, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Dec 06, 2017
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Grzegorz Daniluk authored
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- Dec 04, 2017
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Grzegorz Daniluk authored
compiled from commit: a9add108 Merge branch 'adam-lldp-rebased' into proposed_master
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Compiled from wrpc-sw commit: c0e116b: simpler sdbfs creation by using parameters provided by Syscon HDL module
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Nov 30, 2017
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Grzegorz Daniluk authored
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- Nov 24, 2017
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Grzegorz Daniluk authored
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The streamer has a new start-up delay counter. this delay needs to be shorter for simulation. the fact that we are running simulation was not passed to the Tx streamer, now it is passed.
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by default, the bram content for synthesis is specified. it is only overriden by simulation. In this way, if the top can be both, simulated and synthesized.
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The binary did not work. I do not know why. I just recompiled wrpc-sw with wrpc_sim_defconfig configuration and it works.
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- Aug 25, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 18, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 17, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 16, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 10, 2017
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Grzegorz Daniluk authored
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- Aug 08, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Jul 07, 2017
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
compiled from commit: 25f814a update ppsi to fix 1-pps generation in Master mode
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- Jul 06, 2017
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Maciej Lipinski authored
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Grzegorz Daniluk authored
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- Jul 04, 2017
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Grzegorz Daniluk authored
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