This reverts commit 2349460e.

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Remove internal component declarations, remove unused signals.
Fix names

In wrpc-v5, LM32 is replaced by RISC-V. Hence, the new compiled WRPC software
for the simulation is added (wrc.bram file).
Also, the size of the RAM used by the WRPC software is increased.
The testbench sets hdl_testbench structure used for communication with the software.
The simulation works with ModelSim.

wr_softpll_ng: improved CDC logic. Fixes rare no-locks/FIFO errors, likely due to synthesizer doing some weird cross-clock-domains logic optimizations

... with the input clock

Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

wr_core: add generic for reverse DDMTD operation
wr_gtx_phy_kintex7_lp: make 'reversed' DDMTD operation a generic

Remove unused led_green and led_red, regenerate
Generate H header with struct (instead of offsets)

to ease connection with records

To ease the use of the record variants

Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

timing/pulse_stamper: replace hand-written CDC chains with gc_[sync|pulse_synchronizer] for the ease of constraint definition

Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

wr_softpll_ng: remove builtin frequency monitor, as the WRPCv5 will have a full blown FreqMon core integrated

Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

it has never been really finished to be useful

timing: add enable (mask) input to dmtd_sampler

Forgot to do that when porting the MDIO stuff to Cheby. Sorry Tristan :/

Tomasz Wlostowski authored 1 year ago and Tristan Gingold committed 1 year ago

- we now use Cheby for the MDIO register layout (small changes in the naming)
- dropped LPC_CTRL/LPC_STAT registers in favour of a full WB master interface to the PHY.