wr_core: follow up LPDC/MDIO interface changes of the WR Endpoint

modules/wrc_core/wr_core.vhd

@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
--- Last update: 2023-05-02
+-- Last update: 2023-05-05
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -175,8 +175,17 @@ entity wr_core is
     phy_sfp_tx_disable_o : out std_logic;
 
     phy_rx_rbclk_sampled_i : in std_logic;
-    phy_lpc_stat_i       : in std_logic_vector(15 downto 0);
-    phy_lpc_ctrl_o       : out std_logic_vector(15 downto 0);
+
+    -- clk_sys_i domain!
+    phy_mdio_master_cyc_o : out std_logic;
+    phy_mdio_master_stb_o : out std_logic;
+    phy_mdio_master_we_o : out std_logic;
+    phy_mdio_master_dat_o : out std_logic_vector(31 downto 0);
+    phy_mdio_master_sel_o : out std_logic_vector(3 downto 0) := "0000";
+    phy_mdio_master_adr_o : out std_logic_vector(31 downto 0);
+    phy_mdio_master_ack_i : in std_logic := '0';
+    phy_mdio_master_stall_i : in std_logic := '0';
+    phy_mdio_master_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
 
 
     -- PHY I/F record-based
@@ -508,6 +517,9 @@ architecture struct of wr_core is
   constant c_NUM_FREQMON_CLOCKS: integer := f_count_freqmon_clocks;
 
   signal freqmon_in : std_logic_vector(c_NUM_FREQMON_CLOCKS - 1 downto 0);
+
+  signal phy_mdio_master_out : t_wishbone_master_out;
+  signal phy_mdio_master_in : t_wishbone_master_in;
 begin
 
   -----------------------------------------------------------------------------
@@ -763,9 +775,10 @@ begin
       phy_rx_k_i           => phy_rx_k_i,
       phy_rx_enc_err_i     => phy_rx_enc_err_i,
       phy_rx_bitslide_i    => phy_rx_bitslide_i,
-      phy_lpc_stat_i       => phy_lpc_stat_i,
-      phy_lpc_ctrl_o       => phy_lpc_ctrl_o,
 
+      phy_mdio_master_o => phy_mdio_master_out,
+      phy_mdio_master_i => phy_mdio_master_in,
+            
       phy8_o  => phy8_o,
       phy8_i  => phy8_i,
       phy16_o => phy16_o,
@@ -800,6 +813,18 @@ begin
 
   phy_rst_o <= phy_rst;
 
+  phy_mdio_master_cyc_o <= phy_mdio_master_out.cyc;
+  phy_mdio_master_stb_o <= phy_mdio_master_out.stb;
+  phy_mdio_master_we_o <= phy_mdio_master_out.we;
+  phy_mdio_master_adr_o <= phy_mdio_master_out.adr;
+  phy_mdio_master_sel_o <= phy_mdio_master_out.sel;
+  phy_mdio_master_dat_o <= phy_mdio_master_out.dat;
+  phy_mdio_master_in.dat <= phy_mdio_master_dat_i;
+  phy_mdio_master_in.ack <= phy_mdio_master_ack_i;
+  phy_mdio_master_in.stall <= phy_mdio_master_stall_i;
+  phy_mdio_master_in.rty <= '0';
+  phy_mdio_master_in.err <= '0'; 
+  
   -----------------------------------------------------------------------------
   -- Mini-NIC
   -----------------------------------------------------------------------------

modules/wrc_core/wrcore_pkg.vhd

@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-05-11
--- Last update: 2023-05-02
+-- Last update: 2023-05-05
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -472,10 +472,9 @@ package wrcore_pkg is
       phy_sfp_los_i        : in std_logic := '0';
       phy_sfp_tx_disable_o : out std_logic;
       phy_rx_rbclk_sampled_i : in std_logic := '0';
-
-      phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
-      phy_lpc_stat_i : in std_logic_vector(15 downto 0) := x"0000";
-
+      phy_mdio_master_o : out t_wishbone_master_out;
+      phy_mdio_master_i : in t_wishbone_master_in := cc_dummy_slave_out; 
+    
       -----------------------------------------
       -- PHY I/f - record-based
       -- selection done with g_records_for_phy
@@ -655,8 +654,17 @@ package wrcore_pkg is
       phy_sfp_tx_disable_o : out std_logic;
 
       phy_rx_rbclk_sampled_i : in std_logic := '0';
-      phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
-      phy_lpc_stat_i : in std_logic_vector(15 downto 0) := x"0000";
+
+      -- clk_sys_i domain!
+      phy_mdio_master_cyc_o : out std_logic;
+      phy_mdio_master_stb_o : out std_logic;
+      phy_mdio_master_we_o : out std_logic;
+      phy_mdio_master_dat_o : out std_logic_vector(31 downto 0);
+      phy_mdio_master_sel_o : out std_logic_vector(3 downto 0) := "0000";
+      phy_mdio_master_adr_o : out std_logic_vector(31 downto 0);
+      phy_mdio_master_ack_i : in std_logic := '0';
+      phy_mdio_master_stall_i : in std_logic := '0';
+      phy_mdio_master_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
 
       -----------------------------------------
       -- PHY I/f - record-based

modules/wrc_core/xwr_core.vhd

@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
--- Last update: 2023-05-02
+-- Last update: 2023-05-05
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -166,9 +166,9 @@ entity xwr_core is
     phy_rx_enc_err_i     : in std_logic;
     phy_rx_bitslide_i    : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
 
-    phy_lpc_stat_i       : in std_logic_vector(15 downto 0);
-    phy_lpc_ctrl_o       : out std_logic_vector(15 downto 0);
-    
+    phy_mdio_master_o : out t_wishbone_master_out;
+    phy_mdio_master_i : in t_wishbone_master_in := cc_dummy_slave_out; 
+
     phy_rst_o            : out std_logic;
     phy_rdy_i            : in  std_logic := '1';
     phy_loopen_o         : out std_logic;
@@ -360,13 +360,21 @@ begin
       phy_rdy_i            => phy_rdy_i,
       phy_loopen_o         => phy_loopen_o,
       phy_loopen_vec_o     => phy_loopen_vec_o,
-      phy_lpc_ctrl_o => phy_lpc_ctrl_o,
-      phy_lpc_stat_i => phy_lpc_stat_i,
       phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
       phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
       phy_sfp_los_i        => phy_sfp_los_i,
       phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
 
+      phy_mdio_master_cyc_o  => phy_mdio_master_o.cyc,
+      phy_mdio_master_stb_o  => phy_mdio_master_o.stb,
+      phy_mdio_master_we_o   => phy_mdio_master_o.we,
+      phy_mdio_master_sel_o  => phy_mdio_master_o.sel,
+      phy_mdio_master_adr_o  => phy_mdio_master_o.adr,
+      phy_mdio_master_dat_o    => phy_mdio_master_o.dat,
+      phy_mdio_master_dat_i    => phy_mdio_master_i.dat,
+      phy_mdio_master_stall_i  => phy_mdio_master_i.stall,
+      phy_mdio_master_ack_i    => phy_mdio_master_i.ack,
+
       phy8_o     => phy8_o,
       phy8_i     => phy8_i,
       phy16_o    => phy16_o,