- Jul 20, 2023
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Tristan Gingold authored
boards: fix incorrect logic of reset input for aasd See merge request !8
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Tristan Gingold authored
The arst_i input of gc_reset_multi_aasd is active high, so the resets must be or-ed (using positive logic)
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- Jun 14, 2023
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Tristan Gingold authored
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- Jun 12, 2023
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Tristan Gingold authored
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Tristan Gingold authored
Remove unused led_green and led_red, regenerate Generate H header with struct (instead of offsets)
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
to ease connection with records
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Tristan Gingold authored
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- Jun 09, 2023
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Tristan Gingold authored
Peter lpdc mdio regs generalize See merge request !7
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- Jun 07, 2023
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
Avoid the generation of a latch during synthesis See merge request !2
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Tristan Gingold authored
expose phy_mdio_master interface on xwrc_board_common See merge request !6
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Peter Jansweijer authored
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- Jun 05, 2023
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Tristan Gingold authored
To ease the use of the record variants
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timing/pulse_stamper: replace hand-written CDC chains with gc_[sync|pulse_synchronizer] for the ease of constraint definition
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wr_softpll_ng: remove builtin frequency monitor, as the WRPCv5 will have a full blown FreqMon core integrated
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it has never been really finished to be useful timing: add enable (mask) input to dmtd_sampler
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- May 22, 2023
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Tristan Gingold authored
wr_gtx_phy_virtex6_lp: increase link down detect threshold so the LPDC PHY does… See merge request !5
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- May 17, 2023
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Tomasz Wlostowski authored
wr_gtx_phy_virtex6_lp: increase link down detect threshold so the LPDC PHY does not fail on jumbo frames
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- May 11, 2023
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Tristan Gingold authored
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Tristan Gingold authored
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- May 09, 2023
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
Forgot to do that when porting the MDIO stuff to Cheby. Sorry Tristan :/
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Tristan Gingold authored
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- May 05, 2023
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- we now use Cheby for the MDIO register layout (small changes in the naming) - dropped LPC_CTRL/LPC_STAT registers in favour of a full WB master interface to the PHY.
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wr_endpoint: assume Endpoint's private sub-cores are always present. No need to declare them as components.
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Kintex7 LPDC now has a proper WB interface for the LPDC/Xilinx DRP registers. Follow up in the Endpoint/PCS HDL in the subsequent commits
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