I2C 3-state buffers moved within submodule.

AXI4 slave input interface default values are set and interface is kept in reset by default to allow not connecting this port.

Fix further potential timing issues by defining clocks as asyn

Manifest file overwritten by original CaenELS version.

wr_board_pkg: declare eb_ethernet_slave as a component so that compiler doesn't complain when EB repo is not included