WIP on PHY simulation model

sim/if_wishbone_accessor.svh

@@ -5,7 +5,6 @@
 
 virtual class CWishboneAccessor extends CBusAccessor;
 
-   static int _null  = 0;
    protected wb_cycle_type_t m_cycle_type;
 
    function new();
@@ -45,12 +44,12 @@ virtual class CWishboneAccessor extends CBusAccessor;
 
 
    // [slave only] gets a cycle from the queue
-   virtual task get(ref wb_cycle_t xfer);
+   virtual task get(inout wb_cycle_t xfer);
       
    endtask // get
 
    // [master only] executes a cycle and returns its result
-   virtual task put(ref wb_cycle_t xfer);
+   virtual task put(inout wb_cycle_t xfer);
 
    endtask // put
    
@@ -59,7 +58,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
    endfunction // idle
    
    // [master only] generic write(s), blocking
-   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);
+   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, inout int result );
       wb_cycle_t cycle;
       int i;
 
@@ -84,7 +83,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
    endtask // write
 
    // [master only] generic read(s), blocking
-   virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);
+   virtual task readm(uint64_t addr[], inout uint64_t data[], input int size = 4, inout int result);
       wb_cycle_t cycle;
       int i;
 
@@ -109,7 +108,8 @@ virtual class CWishboneAccessor extends CBusAccessor;
 
    endtask // readm
 
-   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+   virtual task read(uint64_t addr, output uint64_t data, input int size = 4);
+    int result;
       uint64_t aa[], da[];
       aa     = new[1];
       da     = new[1];
@@ -118,7 +118,8 @@ virtual class CWishboneAccessor extends CBusAccessor;
       data  = da[0];
    endtask
 
-   virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);
+   virtual task write(uint64_t addr, uint64_t data, int size = 4);
+    int result;
       uint64_t aa[], da[];
       aa     = new[1];
       da     = new[1];

sim/simdrv_defs.svh

-`ifndef SIMDRV_DEFS_SV
+ `ifndef SIMDRV_DEFS_SV
  `define SIMDRV_DEFS_SV 1
 
 typedef longint unsigned uint64_t;
@@ -14,7 +14,7 @@ typedef byte byte_array_t[];
 
 
 virtual class CBusAccessor;
-   static int _null  = 0;
+
    int        m_default_xfer_size;
    
 
@@ -24,10 +24,10 @@ virtual class CBusAccessor;
    
    
    
-   pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
-   pure virtual task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
+   pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, inout int result);
+   pure virtual task readm(uint64_t addr[], inout uint64_t data[], input int size, inout int result);
 
-   virtual task read(uint64_t addr, ref uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
+   virtual task read(uint64_t addr, output uint64_t data, input int size = 4);
       int res;
       uint64_t aa[1], da[];
 
@@ -39,11 +39,12 @@ virtual class CBusAccessor;
    endtask
 
 
-   virtual task write(uint64_t addr, uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
+   virtual task write(uint64_t addr, uint64_t data, input int size = 4);
+      int res;
       uint64_t aa[1], da[1];
       aa[0]  = addr;
       da[0]  = data;
-      writem(aa, da, size, result);
+      writem(aa, da, size, res);
    endtask
 
 endclass // CBusAccessor
@@ -108,5 +109,5 @@ endclass // CSimUtils
 static CSimUtils SimUtils;
 
 
+`endif
 
-`endif
\ No newline at end of file

sim/wr_1000basex_phy_model.svh

@@ -316,7 +316,7 @@ module wr_1000basex_phy_model
    assign ser_rx = loopen_i ? ser_tx : pad_rxp_i;
 
    assign pad_txp_o = loopen_i == 1'b1 ? 1'bz : ser_tx;
-   assign pad_txn_o = loopen_i == 1'b1? 1'bz : ~ser_tx;
+   assign pad_txn_o = loopen_i == 1'b1 ? 1'bz : ~ser_tx;
    
    
 endmodule // wr_1000basex_phy_model