Allow support of generic platforms

This reverts commit 2349460e.

This reverts commit 2349460e.

Most files changes due to change from LM32 to URV

fasec ip - fix constraints but comment clk_gtx_tx create_generated_clock cause of critical warning ..no logical path from master clock..

Not obvious and if not done, file type is 'unknown' and not available
later on for the loader. See Xilinx support article 71226.

fasec - fix IP files path, have to be relative wrt component.xml; ignoring vivado warning that all files should be below the IP xml

Instead of generating the 62.5MHz DMTD clock using a process, divide an incoming
125MHz clock by 2 using a BUFR on 7Series FPGA (similarly to the Ultrascale+
path).

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>