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Commit 0d27d66b authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
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platform/xilinx: remove unused gthe4 files

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platform/xilinx/wr_gtp_phy/Manifest.py
+ 2
− 6
View file @ 0d27d66b
......@@ -29,6 +29,7 @@ xilinx_ip_gthe4 = [
"xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v"
];
# Common files between gthe3 and gthe4
xilinx_ip_common = [
"xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v",
"xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
......@@ -162,13 +163,8 @@ elif (syn_device[0:4].upper()=="XCKU"): # Kintex Ultrascale GTH
files.extend( xilinx_ip_gthe3 );
files.extend( xilinx_ip_common );
elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
files.extend(["family7-gthe4/wr_gthe4_phy_family7.vhd",
files.extend([
"family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd",
"family7-gthe4/wr_gthe4_reset.vhd",
"family7-gthe4/wr_gthe4_rx_buffer_bypass.vhd",
"family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd",
"family7-gthe4/wr_gthe4_wrapper.vhd",
"family7-gthe4/gc_reset_synchronizer.vhd",
]);
files.extend( xilinx_ip_gthe4 );
files.extend( xilinx_ip_common );
......
platform/xilinx/wr_gtp_phy/family7-gthe4/gc_reset_synchronizer.vhd deleted 100644 → 0
+ 0
− 46
View file @ f7a94147
library ieee;
use ieee.std_logic_1164.all;
entity gc_reset_synchronizer is
generic (
g_reset_active_out : std_logic := '0');
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
rst_synced_o : out std_logic);
end gc_reset_synchronizer;
architecture rtl of gc_reset_synchronizer is
signal gc_sync_ffs_sync0, gc_sync_ffs_sync1, gc_sync_ffs_sync2 : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of gc_sync_ffs_sync0 : signal is "no";
attribute shreg_extract of gc_sync_ffs_sync1 : signal is "no";
attribute keep : string;
attribute keep of gc_sync_ffs_sync0 : signal is "true";
attribute keep of gc_sync_ffs_sync1 : signal is "true";
-- synchronizer attribute for Vivado
attribute ASYNC_REG : string;
attribute ASYNC_REG of gc_sync_ffs_sync0 : signal is "true";
attribute ASYNC_REG of gc_sync_ffs_sync1 : signal is "true";
begin
process(clk_i, rst_n_a_i)
begin
if(rst_n_a_i = '0') then
gc_sync_ffs_sync0 <= '0';
gc_sync_ffs_sync1 <= '0';
gc_sync_ffs_sync2 <= '0';
rst_synced_o <= g_reset_active_out;
elsif rising_edge(clk_i) then
gc_sync_ffs_sync0 <= not rst_n_a_i;
gc_sync_ffs_sync1 <= gc_sync_ffs_sync0;
rst_synced_o <= gc_sync_ffs_sync1;
end if;
end process;
end rtl;
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7.vhd deleted 100644 → 0
+ 0
− 505
View file @ f7a94147
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity wr_gthe4_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0;
g_use_gclk_as_refclk : boolean := true
);
port (
-- Dedicated reference 125 MHz clock for the GTX transceiver
-- clk_gth_p_i : in std_logic;
-- clk_gth_n_i : in std_logic;
clk_gth_i : in std_logic;
-- GCLK 125M refrence
clk_gth_gclk_i : in std_logic := '0';
clk_freerun_i : in std_logic;
-- TX path, synchronous to tx_out_clk_o (62.5 MHz):
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(15 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(4 downto 0);
-- reset input, active hi
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
debug_i : in std_logic_vector(15 downto 0);
debug_o : out std_logic_vector(15 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end wr_gthe4_phy_family7;
architecture rtl of wr_gthe4_phy_family7 is
component BUFG_GT_SYNC is
port (
CESYNC : out std_ulogic;
CLRSYNC : out std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
CLR : in std_ulogic);
end component BUFG_GT_SYNC;
component BUFG_GT is
port (
O : out std_ulogic;
CE : in std_ulogic;
CEMASK : in std_ulogic;
CLR : in std_ulogic;
CLRMASK : in std_ulogic;
DIV : in std_logic_vector(2 downto 0);
I : in std_ulogic);
end component BUFG_GT;
component IBUFDS_GTE3 is
generic (
REFCLK_EN_TX_PATH : bit;
REFCLK_HROW_CK_SEL : std_logic_vector (1 downto 0);
REFCLK_ICNTL_RX : std_logic_vector (1 downto 0));
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component IBUFDS_GTE3;
signal GTGREFCLK : std_logic;
signal CPLLPD : std_logic;
signal CPLLLOCK : std_logic;
signal RXCDRLOCK : std_logic;
signal RXRESETDONE : std_logic;
signal GTRXRESET : std_logic;
signal GTTXRESET : std_logic;
signal TXRESETDONE : std_logic;
signal TXPROGDIVRESET : std_logic;
signal GTHTXN : std_logic;
signal GTHTXP : std_logic;
signal GTPOWERGOOD : std_logic;
signal RXBYTEISALIGNED : std_logic;
signal RXCOMMADET : std_logic;
signal RXCTRL0 : std_logic_vector(15 downto 0);
signal RXCTRL3 : std_logic_vector(7 downto 0);
signal RXDATA : std_logic_vector(127 downto 0);
signal RXOUTCLK : std_logic;
signal RXPHALIGNDONE : std_logic;
signal RXPMARESETDONE : std_logic;
signal RXSYNCDONE : std_logic;
signal TXOUTCLK : std_logic;
signal TXPHALIGNDONE : std_logic;
signal TXPMARESETDONE : std_logic;
signal TXSYNCDONE : std_logic;
signal DRPCLK : std_logic;
signal GTHRXN : std_logic;
signal GTHRXP : std_logic;
signal GTREFCLK0 : std_logic;
signal RXPROGDIVRESET : std_logic;
signal RXSLIDE : std_logic;
signal RXSYNCALLIN : std_logic;
signal RXUSERRDY : std_logic;
signal RXUSRCLK2 : std_logic;
signal TXCTRL2 : std_logic_vector(7 downto 0);
signal TXDATA : std_logic_vector(127 downto 0);
signal TXDLYSRESET : std_logic;
signal TXSYNCALLIN : std_logic;
signal TXUSERRDY : std_logic;
signal TXUSRCLK2 : std_logic;
signal RXDLYSRESET : std_logic;
signal serdes_ready : std_logic;
signal rx_synced, rst_rxclk : std_logic;
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_err_int : std_logic_vector(1 downto 0);
signal serdes_ready_txusrclk, serdes_ready_rxusrclk : std_logic;
signal cur_disp : t_8b10b_disparity;
signal rx_active : std_logic;
signal tx_active : std_logic;
signal reset_done : std_logic;
signal TXPMARESETDONE_n, RXPMARESETDONE_n : std_logic;
signal tx_clk_CESYNC, rx_clk_CESYNC : std_logic;
signal tx_clk_CLRSYNC, rx_clk_CLRSYNC : std_logic;
signal rst_master_n : std_logic;
signal tx_buffer_bypass_done : std_logic;
signal rx_buffer_bypass_done : std_logic;
signal rx_pcs_reset : std_logic;
function f_is_synthesis return boolean is
begin
-- synthesis translate_off
return false;
-- synthesis translate_on
return true;
end function;
attribute mark_debug : string;
attribute mark_debug of CPLLPD : signal is "TRUE";
attribute mark_debug of CPLLLOCK : signal is "TRUE";
attribute mark_debug of GTRXRESET : signal is "TRUE";
attribute mark_debug of GTTXRESET : signal is "TRUE";
attribute mark_debug of TXRESETDONE : signal is "TRUE";
attribute mark_debug of TXPROGDIVRESET : signal is "TRUE";
attribute mark_debug of RXCDRLOCK : signal is "TRUE";
attribute mark_debug of RXCOMMADET : signal is "TRUE";
attribute mark_debug of RXPHALIGNDONE : signal is "TRUE";
attribute mark_debug of RXSYNCDONE : signal is "TRUE";
attribute mark_debug of TXPHALIGNDONE : signal is "TRUE";
attribute mark_debug of TXPMARESETDONE : signal is "TRUE";
attribute mark_debug of TXSYNCDONE : signal is "TRUE";
attribute mark_debug of RXPROGDIVRESET : signal is "TRUE";
attribute mark_debug of RXSLIDE : signal is "TRUE";
attribute mark_debug of RXSYNCALLIN: signal is "TRUE";
attribute mark_debug of RXUSERRDY : signal is "TRUE";
attribute mark_debug of TXDLYSRESET: signal is "TRUE";
attribute mark_debug of TXSYNCALLIN: signal is "TRUE";
attribute mark_debug of TXUSERRDY : signal is "TRUE";
attribute mark_debug of RST_I : signal is "TRUE";
attribute mark_debug of tx_k_i : signal is "TRUE";
attribute mark_debug of tx_DATA_i : signal is "TRUE";
attribute mark_debug of RX_k_o : signal is "TRUE";
attribute mark_debug of rx_DATA_o : signal is "TRUE";
attribute mark_debug of serdes_ready : signal is "TRUE";
attribute mark_debug of tx_active : signal is "TRUE";
attribute mark_debug of rx_active : signal is "TRUE";
attribute mark_debug of reset_done : signal is "TRUE";
begin
rst_master_n <= not rst_i;
TXCTRL2(7 downto 2) <= (others => '0');
TXCTRL2(1) <= tx_k_i(0);
TXCTRL2(0) <= tx_k_i(1);
TXDATA(7 downto 0) <= tx_data_i(15 downto 8);
TXDATA(15 downto 8) <= tx_data_i(7 downto 0);
TXDATA(127 downto 16) <= (others => '0');
rx_k_int <= RXCTRL0(1 downto 0);
rx_err_int <= RXCTRL3(1 downto 0);
rx_data_int <= RXDATA(15 downto 0);
U_Bitslide : entity work.gtp_bitslide
generic map (
g_simulation => g_simulation,
g_target => "ultrascale")
port map (
gtp_rst_i => rst_i,
gtp_rx_clk_i => RXUSRCLK2,
gtp_rx_comma_det_i => RXCOMMADET,
gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED,
serdes_ready_i => serdes_ready_rxusrclk,
gtp_rx_slide_o => RXSLIDE,
gtp_rx_cdr_rst_o => rx_pcs_reset,
bitslide_o => rx_bitslide_o,
synced_o => rx_synced);
gen_use_dedicated_clock : if g_use_gclk_as_refclk = false generate
-- U_Ref_Clock_Buffer : IBUFDS_GTE4
-- generic map (
-- REFCLK_EN_TX_PATH => '0',
-- REFCLK_HROW_CK_SEL => "00",
-- REFCLK_ICNTL_RX => "00")
-- port map (
-- O => GTREFCLK0,
-- ODIV2 => open,
-- CEB => '0',
-- I => clk_gth_p_i,
-- IB => clk_gth_n_i);
GTREFCLK0 <= clk_gth_i;
GTGREFCLK <= '0';
end generate gen_use_dedicated_clock;
gen_use_gclk : if g_use_gclk_as_refclk = true generate
GTREFCLK0 <= '0';
GTGREFCLK <= clk_gth_gclk_i;
end generate gen_use_gclk;
U_Sync_TX_Clock_Reset : BUFG_GT_SYNC
port map (
CESYNC => tx_clk_CESYNC,
CLRSYNC => tx_clk_CLRSYNC,
CE => '1',
CLK => TXOUTCLK,
CLR => TXPMARESETDONE_n);
TXPMARESETDONE_n <= not TXPMARESETDONE;
U_TX_Clock_Buffer : BUFG_GT port map
(
CE => tx_clk_CESYNC,
CEMASK => '0',
CLR => tx_clk_CLRSYNC,
CLRMASK => '0',
DIV => "001",
I => TXOUTCLK,
O => TXUSRCLK2
);
U_Sync_RX_Clock_Reset : BUFG_GT_SYNC
port map (
CESYNC => rx_clk_CESYNC,
CLRSYNC => rx_clk_CLRSYNC,
CE => '1',
CLK => RXOUTCLK,
CLR => RXPMARESETDONE_n);
RXPMARESETDONE_n <= not RXPMARESETDONE;
U_RX_Clock_Buffer : BUFG_GT port map
(
CE => rx_clk_CESYNC,
CEMASK => '0',
CLR => rx_clk_CLRSYNC,
CLRMASK => '0',
DIV => "000",
I => RXOUTCLK,
O => RXUSRCLK2
);
U_GenRXActive_Reset : gc_sync_ffs
port map (
clk_i => RXUSRCLK2,
rst_n_i => rst_master_n,
data_i => '1',
synced_o => rx_active);
U_GenTXActive_Reset : gc_sync_ffs
port map (
clk_i => TXUSRCLK2,
rst_n_i => rst_master_n,
data_i => '1',
synced_o => tx_active);
U_TX_Buffer_Bypass : entity work.wr_gthe4_tx_buffer_bypass
port map (
clk_free_i => clk_freerun_i,
rst_i => rst_i,
TXUSRCLK2_i => TXUSRCLK2,
TXRESETDONE_i => TXRESETDONE,
TXDLYSRESET_o => TXDLYSRESET,
TXSYNCDONE_i => TXSYNCDONE,
done_o => tx_buffer_bypass_done);
U_RX_Buffer_Bypass : entity work.wr_gthe4_rx_buffer_bypass
port map (
clk_free_i => clk_freerun_i,
rst_i => rst_i,
RXUSRCLK2_i => RXUSRCLK2,
RXRESETDONE_i => RXRESETDONE,
RXDLYSRESET_o => RXDLYSRESET,
RXSYNCDONE_i => RXSYNCDONE,
done_o => rx_buffer_bypass_done);
U_Sync_Ready_RXClk : gc_sync_ffs
port map (
clk_i => RXUSRCLK2,
rst_n_i => rst_master_n,
data_i => serdes_ready,
synced_o => serdes_ready_rxusrclk);
U_Sync_Ready_TXClk : gc_sync_ffs
port map (
clk_i => TXUSRCLK2,
rst_n_i => rst_master_n,
data_i => serdes_ready,
synced_o => serdes_ready_txusrclk);
serdes_ready <= reset_done and rx_buffer_bypass_done and tx_buffer_bypass_done and RXRESETDONE and TXRESETDONE and TXSYNCDONE and RXSYNCDONE and RXPMARESETDONE and TXPMARESETDONE;
-- tx_active -> userclk_tx_reset and deassert tx_active on rst master, deassert after few cycles of
-- txusrclk2. same for rx_active.
U_Reset_FSM : entity work.wr_gthe4_reset
port map (
rst_i => rst_i,
clk_free_i => clk_freerun_i,
CPLLPD_o => CPLLPD,
CPLLLOCK_i => CPLLLOCK,
RXCDRLOCK_i => RXCDRLOCK,
RXRESETDONE_i => RXRESETDONE,
GTRXRESET_o => GTRXRESET,
TXUSERRDY_o => TXUSERRDY,
RXPROGDIVRESET_o => RXPROGDIVRESET,
GTTXRESET_o => GTTXRESET,
TXRESETDONE_i => TXRESETDONE,
TXPROGDIVRESET_o => TXPROGDIVRESET,
RXUSERRDY_o => RXUSERRDY,
rx_active_i => rx_active,
tx_active_i => tx_active,
done_o => reset_done);
U_Wrapped_GTHE4 : entity work.wr_gthe4_wrapper
generic map (
g_use_gclk_as_refclk => g_use_gclk_as_refclk
)
port map (
GTGREFCLK => GTGREFCLK,
CPLLPD => CPLLPD,
CPLLLOCK => CPLLLOCK,
RXCDRLOCK => RXCDRLOCK,
RXRESETDONE => RXRESETDONE,
GTRXRESET => GTRXRESET,
RXPROGDIVRESET => RXPROGDIVRESET,
GTTXRESET => GTTXRESET,
TXRESETDONE => TXRESETDONE,
TXPROGDIVRESET => TXPROGDIVRESET,
GTHTXN => GTHTXN,
GTHTXP => GTHTXP,
GTPOWERGOOD => GTPOWERGOOD,
RXBYTEISALIGNED => RXBYTEISALIGNED,
RXCOMMADET => RXCOMMADET,
RXCTRL0 => RXCTRL0,
RXPCSRESET => rx_pcs_reset,
rxctrl3 => rxctrl3,
RXDATA => RXDATA,
RXOUTCLK => RXOUTCLK,
RXPHALIGNDONE => RXPHALIGNDONE,
RXPMARESETDONE => RXPMARESETDONE,
RXSYNCDONE => RXSYNCDONE,
TXOUTCLK => TXOUTCLK,
TXPHALIGNDONE => TXPHALIGNDONE,
TXPMARESETDONE => TXPMARESETDONE,
TXSYNCDONE => TXSYNCDONE,
DRPCLK => DRPCLK,
GTHRXN => GTHRXN,
GTHRXP => GTHRXP,
GTREFCLK0 => GTREFCLK0,
RXDLYSRESET => RXDLYSRESET,
RXSLIDE => RXSLIDE,
RXSYNCALLIN => RXSYNCALLIN,
RXUSERRDY => RXUSERRDY,
RXUSRCLK2 => RXUSRCLK2,
TXCTRL2 => TXCTRL2,
TXDATA => TXDATA,
TXDLYSRESET => TXDLYSRESET,
TXSYNCALLIN => TXSYNCALLIN,
TXUSERRDY => TXUSERRDY,
TXUSRCLK2 => TXUSRCLK2);
DRPCLK <= clk_freerun_i;
TXSYNCALLIN <= TXPHALIGNDONE;
RXSYNCALLIN <= RXPHALIGNDONE;
pad_txn_o <= GTHTXN;
pad_txp_o <= GTHTXP;
GTHRXN <= pad_rxn_i;
GTHRXP <= pad_rxp_i;
p_gen_rx_outputs : process(RXUSRCLK2, serdes_ready_rxusrclk)
begin
if(serdes_ready_rxusrclk = '0') then
rx_data_o <= (others => '0');
rx_k_o <= (others => '0');
rx_enc_err_o <= '1';
elsif rising_edge(RXUSRCLK2) then
if(serdes_ready_rxusrclk = '1' and rx_synced = '1' and rx_err_int = "00") then
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= '0'; --rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end process;
p_gen_tx_disparity : process(TXUSRCLK2)
begin
if rising_edge(TXUSRCLK2) then
if serdes_ready_txusrclk = '0' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
gen_simulation : if not f_is_synthesis generate
tx_out_clk_o <= TXUSRCLK2 after 0.5 ns;
rx_rbclk_o <= RXUSRCLK2 after 0.5 ns;
end generate gen_simulation;
gen_synthesis : if f_is_synthesis generate
tx_out_clk_o <= TXUSRCLK2;
rx_rbclk_o <= RXUSRCLK2;
end generate gen_synthesis;
rdy_o <= serdes_ready;
tx_locked_o <= serdes_ready;
tx_enc_err_o <= '0';
end rtl;
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_reset.vhd deleted 100644 → 0
+ 0
− 238
View file @ f7a94147
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity wr_gthe4_reset is
port (
rst_i : in std_logic;
clk_free_i : in std_logic;
-- CPLL reset I/O
CPLLPD_o : out std_logic;
CPLLLOCK_i : in std_logic;
-- RX path resets
RXCDRLOCK_i : in std_logic;
RXRESETDONE_i : in std_logic;
GTRXRESET_o : out std_logic;
RXPROGDIVRESET_o : out std_logic;
RXUSERRDY_o : out std_logic;
-- TX path resets
GTTXRESET_o : out std_logic;
TXRESETDONE_i : in std_logic;
TXPROGDIVRESET_o : out std_logic;
TXUSERRDY_o : out std_logic;
rx_active_i : in std_logic;
tx_active_i : in std_logic;
done_o : out std_logic
);
end wr_gthe4_reset;
architecture rtl of wr_gthe4_reset is
constant c_RESET_TIMEOUT : integer := 1000;
type t_state is (RESTART, DONE, CPLL_WAIT_LOCK, CPLL_RESET_TIMEOUT, CDR_WAIT_LOCK, TX_ACTIVE_WAIT, RX_ACTIVE_WAIT, TX_RESET_DONE_WAIT, RX_RESET_DONE_WAIT, TX_RESET_TIMER_WAIT);
signal state : t_state;
signal rst_master_clk_free : std_logic;
signal CPLLLOCK_clk_free, tx_active_clk_free : std_logic;
signal rx_active_clk_free : std_logic;
signal TXRESETDONE_clk_free : std_logic;
signal RXRESETDONE_clk_free : std_logic;
signal RXCDRLOCK_clk_free : std_logic;
signal timeout_cnt : unsigned(15 downto 0);
begin
U_SyncResetAll : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => rst_i,
synced_o => rst_master_clk_free);
U_SyncCPLLLOCK : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => CPLLLOCK_i,
synced_o => CPLLLOCK_clk_free);
U_SyncTxActive : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => tx_active_i,
synced_o => tx_active_clk_free);
U_SyncRxActive : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => rx_active_i,
synced_o => rx_active_clk_free);
U_SyncRxResetDone : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => RXRESETDONE_i,
synced_o => RXRESETDONE_clk_free);
U_SyncTxResetDone : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => TXRESETDONE_i,
synced_o => TXRESETDONE_clk_free);
U_SyncRxCdrLock : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => RXCDRLOCK_i,
synced_o => RXCDRLOCK_clk_free);
TXPROGDIVRESET_o <= not CPLLLOCK_clk_free;
-- TX side:
-- - assert pllreset_tx, gttxreset
-- - wait for lock (plllock_tx, pllreset_tx -> 0)
-- - gttxreset -> 0
-- - wait for tx_active
-- - wait for txresetdone
-- - we're done
-- RX side:
-- - assert pllreset_rx, rxprogdivreset, gtrxreset
-- - wait for plllock_rx, pllreset_rx->0
-- - deassert gtrxreset
-- - wait for cdr lock
-- - deassert progdiv reset
-- - wait for rx_active
-- - wait for rxresetdone
-- - we're done
process(clk_free_i)
begin
if rising_edge(clk_free_i)then
if rst_master_clk_free = '1' then
state <= RESTART;
done_o <= '0';
GTTXRESET_o <= '1';
GTRXRESET_o <= '1';
RXPROGDIVRESET_o <= '1';
TXUSERRDY_o <= '0';
RXUSERRDY_o <= '0';
else
done_o <= '0';
case state is
when RESTART =>
CPLLPD_o <= '1'; -- assert both TX and RX PLL reset (we're using the
-- CPLL that serves both)
GTTXRESET_o <= '1';
GTRXRESET_o <= '1';
RXPROGDIVRESET_o <= '1';
TXUSERRDY_o <= '0';
RXUSERRDY_o <= '0';
state <= CPLL_WAIT_LOCK;
timeout_cnt <= to_unsigned(c_RESET_TIMEOUT, 16);
when CPLL_RESET_TIMEOUT =>
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 0 then
CPLLPD_o <= '0';
state <= CPLL_WAIT_LOCK;
end if;
when CPLL_WAIT_LOCK =>
CPLLPD_o <= '0';
if CPLLLOCK_clk_free = '1' then
GTTXRESET_o <= '1';
GTRXRESET_o <= '1';
timeout_cnt <= to_unsigned(c_RESET_TIMEOUT, 16);
state <= TX_RESET_TIMER_WAIT;
end if;
when TX_RESET_TIMER_WAIT =>
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 0 then
GTTXRESET_o <= '0';
GTRXRESET_o <= '0';
state <= TX_ACTIVE_WAIT;
end if;
when TX_ACTIVE_WAIT =>
if tx_active_clk_free = '1' then
state <= TX_RESET_DONE_WAIT;
TXUSERRDY_o <= '1';
end if;
when TX_RESET_DONE_WAIT =>
if TXRESETDONE_clk_free = '1' then
state <= CDR_WAIT_LOCK;
end if;
when CDR_WAIT_LOCK =>
if RXCDRLOCK_clk_free = '1' then
RXPROGDIVRESET_o <= '0';
state <= RX_ACTIVE_WAIT;
end if;
when RX_ACTIVE_WAIT =>
if rx_active_clk_free = '1' then
state <= RX_RESET_DONE_WAIT;
RXUSERRDY_o <= '1';
end if;
when RX_RESET_DONE_WAIT =>
if RXRESETDONE_clk_free = '1' then
state <= DONE;
end if;
when DONE =>
done_o <= '1';
end case;
end if;
end if;
end process;
end rtl;
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_rx_buffer_bypass.vhd deleted 100644 → 0
+ 0
− 99
View file @ f7a94147
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity wr_gthe4_rx_buffer_bypass is
port
(
clk_free_i : in std_logic;
rst_i : in std_logic;
RXUSRCLK2_i : in std_logic;
RXRESETDONE_i : in std_logic;
RXDLYSRESET_o : out std_logic;
RXSYNCDONE_i : in std_logic;
done_o : out std_logic
);
end wr_gthe4_rx_buffer_bypass;
architecture rtl of wr_gthe4_rx_buffer_bypass is
type t_state is (WAIT_RESTART, ASSERT_DLY_RESET, WAIT_SYNC_DONE, DONE);
signal state : t_state;
signal rst_rxusrclk2 : std_logic;
signal RXRESETDONE_clk_free : std_logic;
signal RXSYNCDONE_clk_free_p1 : std_logic;
signal done_int : std_logic;
begin
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => RXUSRCLK2_i,
rst_n_i => '1',
data_i => rst_i,
synced_o => rst_rxusrclk2);
U_Sync_Done : gc_sync_ffs
port map (
clk_i => clk_free_i,
rst_n_i => '1',
data_i => done_int,
synced_o => done_o);
-- RX dly align procedure:
--
-- start on RXRESETDONE
-- rxdlysreset_out = 1
-- rxdlysreset_out = 0
-- wait for RE of rxsyncdone
p_rx_buffer_bypass : process(RXUSRCLK2_i)
begin
if rising_edge(RXUSRCLK2_i) then
if rst_rxusrclk2 = '1' then
state <= WAIT_RESTART;
RXDLYSRESET_o <= '0';
done_int <= '0';
else
RXDLYSRESET_o <= '0';
done_int <= '0';
case state is
when WAIT_RESTART =>
if RXRESETDONE_i = '1' then
state <= ASSERT_DLY_RESET;
end if;
when ASSERT_DLY_RESET =>
RXDLYSRESET_o <= '1';
state <= WAIT_SYNC_DONE;
when WAIT_SYNC_DONE =>
RXDLYSRESET_o <= '0';
if RXSYNCDONE_i = '1' then
state <= DONE;
end if;
when DONE =>
done_int <= '1';
end case;
end if;
end if;
end process;
end rtl;
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd deleted 100644 → 0
+ 0
− 127
View file @ f7a94147
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity wr_gthe4_tx_buffer_bypass is
port
(
clk_free_i : in std_logic;
rst_i : in std_logic;
TXUSRCLK2_i : in std_logic;
TXRESETDONE_i : in std_logic;
TXDLYSRESET_o : out std_logic;
TXSYNCDONE_i : in std_logic;
done_o : out std_logic
);
end wr_gthe4_tx_buffer_bypass;
architecture rtl of wr_gthe4_tx_buffer_bypass is
type t_state is (WAIT_RESTART, ASSERT_DLY_RESET, WAIT_SYNC_DONE, DONE);
signal rst_txusrclk2 : std_logic;
signal TXRESETDONE_clk_txusr : std_logic;
signal TXSYNCDONE_clk_txusr_p1 : std_logic;
signal TXDLYSRESET_int : std_logic;
signal done_int : std_logic;
signal state : t_state;
signal rst_n : std_logic;
begin
rst_n <= not rst_i;
U_Sync_Reset : entity work.gc_reset_synchronizer
generic map (
g_reset_active_out => '1')
port map (
clk_i => TXUSRCLK2_i,
rst_n_a_i => rst_n,
rst_synced_o => rst_txusrclk2);
U_Sync_Done : gc_sync_ffs
port map (
clk_i => clk_free_i,
rst_n_i => rst_n,
data_i => done_int,
synced_o => done_o);
U_Sync_TXRESETDONE : gc_sync_ffs
port map (
clk_i => TXUSRCLK2_i,
rst_n_i => rst_n,
data_i => TXRESETDONE_i,
synced_o => TXRESETDONE_clk_txusr);
U_Sync_TXSYNCDONE : gc_sync_ffs
port map (
clk_i => TXUSRCLK2_i,
rst_n_i => rst_n,
data_i => TXSYNCDONE_i,
ppulse_o => TXSYNCDONE_clk_txusr_p1);
-- TX dly align procedure:
--
-- start on TXRESETDONE
-- txdlysreset_out = 1
-- txdlysreset_out = 0
-- wait for RE of txsyncdone
p_tx_buffer_bypass : process(TXUSRCLK2_i, rst_txusrclk2)
begin
if rst_txusrclk2 = '1' then
state <= WAIT_RESTART;
TXDLYSRESET_int <= '0';
done_int <= '0';
elsif rising_edge(TXUSRCLK2_i) then
if rst_txusrclk2 = '1' then
state <= WAIT_RESTART;
TXDLYSRESET_int <= '0';
done_int <= '0';
else
TXDLYSRESET_int <= '0';
done_int <= '0';
case state is
when WAIT_RESTART =>
if TXRESETDONE_i = '1' then
state <= ASSERT_DLY_RESET;
end if;
when ASSERT_DLY_RESET =>
TXDLYSRESET_int <= '1';
state <= WAIT_SYNC_DONE;
when WAIT_SYNC_DONE =>
TXDLYSRESET_int <= '0';
if TXSYNCDONE_clk_txusr_p1 = '1' then
state <= DONE;
end if;
when DONE =>
done_int <= '1';
end case;
end if;
end if;
end process;
txdlysreset_o <= TXDLYSRESET_int;
end rtl;
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd deleted 100644 → 0
+ 0
− 964
View file @ f7a94147
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