[EP/tx_inj] improved test inj_gen mode configuration (can be changed separately from other config - different valid bit). This was convenient for software control implementation

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

Endpoint-RX_PAUSE: changing configuration to allow enabling both kinds of PAUSE (802.3 and 802.1Q), fixing bug for 802.3 - remembering wrong quanta

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

endpoint: added handling of priority-based Flow Control, exposed information about received PAUSE frames outside Endpoint - to be used by SWcore

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

pFilter: changed simulation driver so that the same mircocode can be nicely loaded many times to many ports

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

bugfix in eth packet simulation class. It was not possible to set pck size at initialization (new function) -- bug fixed

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

Endpoint-pfilter: adding Packet Filter microcode SystemVerilog class by Tom. It is used to program the endpoint pakcet filter

Maciej Lipinski authored 12 years ago and Grzegorz Daniluk committed 11 years ago

endpoint: VLANs related bugfix. Adding extraction of VLAN-tag related info to the rtu_header_extract and correcting VLAN-related packet tx/rx simulation (there was wrong order of VLAN-tag)

When WR PTP Core is set in GrandMaster mode it aligns its nanosecond
counter to 1-PPS and 10MHz coming from external source. When user wants
to set seconds counter to a desired value, the nanosecond counter was
also set (zeroed) causing additional (random) offset to the external
source.

After transmitting a frame in software, the LM32 reads out the
timestamp set by hardware. Naturally, this comes after the frame
has been sent, so the LM32 must wait.

Prior to this patch the only thing it could wait for was DMA idle.
However, DMA of the packet completes before the timestamp is ready.
Thus there was a race condition where the LM32 would see an old TS.

sim/eth_packet.svh: define permament_stall functions as empty instead of pure virtual (Modelsim bug workaround)

Maciej Lipinski authored 13 years ago and Tomasz Wlostowski committed 13 years ago

Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

simulation models: moved abstract packet sink/source classes away from WB-specific implementations to eth_packet.svh

	modified:   endpoint_regs.v
	modified:   minic_regs.vh

modules/mini_bone: uploaded example testbench for WBPacketSink/WBPacketSource with an Etherbone mockup