Skip to content
Snippets Groups Projects
Commit 503fd2cc authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files

wrcore: adding i2c sw master to communicate with sfp module

parent 3435d975
Branches
Tags
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 256 additions and 22 deletions
modules/wrc_core/wr_core.vhd
+ 10
− 1
View file @ 503fd2cc
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
......@@ -117,6 +116,11 @@ entity wr_core is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
......@@ -612,6 +616,11 @@ begin
scl_i => scl_i,
sda_o => sda_o,
sda_i => sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
memsize_i => "0000",
btn1_i => btn1_i,
btn2_i => btn2_i,
......
modules/wrc_core/wrc_periph.vhd
+ 36
− 1
View file @ 503fd2cc
......@@ -51,6 +51,11 @@ entity wrc_periph is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
memsize_i : in std_logic_vector(3 downto 0);
btn1_i : in std_logic;
btn2_i : in std_logic;
......@@ -179,7 +184,7 @@ begin
end process;
-------------------------------------
-- I2C
-- I2C - FMC
-------------------------------------
p_drive_i2c : process(clk_sys_i)
begin
......@@ -206,6 +211,36 @@ begin
sysc_regs_i.gpsr_fmc_sda_i <= sda_i;
sysc_regs_i.gpsr_fmc_scl_i <= scl_i;
-------------------------------------
-- I2C - SFP
-------------------------------------
p_drive_sfpi2c : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sfp_scl_o <= '1';
sfp_sda_o <= '1';
else
if(sysc_regs_o.gpsr_sfp_sda_load_o = '1' and sysc_regs_o.gpsr_sfp_sda_o = '1') then
sfp_sda_o <= '1';
elsif(sysc_regs_o.gpcr_sfp_sda_o = '1') then
sfp_sda_o <= '0';
end if;
if(sysc_regs_o.gpsr_sfp_scl_load_o = '1' and sysc_regs_o.gpsr_sfp_scl_o = '1') then
sfp_scl_o <= '1';
elsif(sysc_regs_o.gpcr_sfp_scl_o = '1') then
sfp_scl_o <= '0';
end if;
end if;
end if;
end process;
sysc_regs_i.gpsr_sfp_sda_i <= sfp_sda_i;
sysc_regs_i.gpsr_sfp_scl_i <= sfp_scl_i;
sysc_regs_i.gpsr_sfp_det_i <= sfp_det_i;
----------------------------------------
-- SYSCON
----------------------------------------
......
modules/wrc_core/wrc_syscon_pkg.vhd
+ 22
− 1
View file @ 503fd2cc
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Nov 30 15:12:21 2011
-- Created : Fri Feb 17 19:23:19 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -24,6 +24,9 @@ package sysc_wbgen2_pkg is
gpsr_fmc_sda_i : std_logic;
gpsr_btn1_i : std_logic;
gpsr_btn2_i : std_logic;
gpsr_sfp_det_i : std_logic;
gpsr_sfp_scl_i : std_logic;
gpsr_sfp_sda_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0);
tcr_tdiv_i : std_logic_vector(11 downto 0);
tvr_i : std_logic_vector(31 downto 0);
......@@ -34,6 +37,9 @@ package sysc_wbgen2_pkg is
gpsr_fmc_sda_i => '0',
gpsr_btn1_i => '0',
gpsr_btn2_i => '0',
gpsr_sfp_det_i => '0',
gpsr_sfp_scl_i => '0',
gpsr_sfp_sda_i => '0',
hwfr_memsize_i => (others => '0'),
tcr_tdiv_i => (others => '0'),
tvr_i => (others => '0')
......@@ -52,10 +58,16 @@ package sysc_wbgen2_pkg is
gpsr_fmc_sda_o : std_logic;
gpsr_fmc_sda_load_o : std_logic;
gpsr_net_rst_o : std_logic;
gpsr_sfp_scl_o : std_logic;
gpsr_sfp_scl_load_o : std_logic;
gpsr_sfp_sda_o : std_logic;
gpsr_sfp_sda_load_o : std_logic;
gpcr_led_stat_o : std_logic;
gpcr_led_link_o : std_logic;
gpcr_fmc_scl_o : std_logic;
gpcr_fmc_sda_o : std_logic;
gpcr_sfp_scl_o : std_logic;
gpcr_sfp_sda_o : std_logic;
tcr_enable_o : std_logic;
end record;
......@@ -70,10 +82,16 @@ package sysc_wbgen2_pkg is
gpsr_fmc_sda_o => '0',
gpsr_fmc_sda_load_o => '0',
gpsr_net_rst_o => '0',
gpsr_sfp_scl_o => '0',
gpsr_sfp_scl_load_o => '0',
gpsr_sfp_sda_o => '0',
gpsr_sfp_sda_load_o => '0',
gpcr_led_stat_o => '0',
gpcr_led_link_o => '0',
gpcr_fmc_scl_o => '0',
gpcr_fmc_sda_o => '0',
gpcr_sfp_scl_o => '0',
gpcr_sfp_sda_o => '0',
tcr_enable_o => '0'
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
......@@ -96,6 +114,9 @@ tmp.gpsr_fmc_scl_i := left.gpsr_fmc_scl_i or right.gpsr_fmc_scl_i;
tmp.gpsr_fmc_sda_i := left.gpsr_fmc_sda_i or right.gpsr_fmc_sda_i;
tmp.gpsr_btn1_i := left.gpsr_btn1_i or right.gpsr_btn1_i;
tmp.gpsr_btn2_i := left.gpsr_btn2_i or right.gpsr_btn2_i;
tmp.gpsr_sfp_det_i := left.gpsr_sfp_det_i or right.gpsr_sfp_det_i;
tmp.gpsr_sfp_scl_i := left.gpsr_sfp_scl_i or right.gpsr_sfp_scl_i;
tmp.gpsr_sfp_sda_i := left.gpsr_sfp_sda_i or right.gpsr_sfp_sda_i;
tmp.hwfr_memsize_i := left.hwfr_memsize_i or right.hwfr_memsize_i;
tmp.tcr_tdiv_i := left.tcr_tdiv_i or right.tcr_tdiv_i;
tmp.tvr_i := left.tvr_i or right.tvr_i;
......
modules/wrc_core/wrc_syscon_regs.h
+ 16
− 1
View file @ 503fd2cc
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Nov 30 15:45:28 2011
* Created : Fri Feb 17 19:23:19 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -65,6 +65,15 @@
/* definitions for field: SPEC Pushbutton 2 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: SFP detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_DET WBGEN2_GEN_MASK(7, 1)
/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -79,6 +88,12 @@
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SDA WBGEN2_GEN_MASK(3, 1)
/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......
modules/wrc_core/wrc_syscon_wb.vhd
+ 60
− 4
View file @ 503fd2cc
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Nov 30 15:12:21 2011
-- Created : Fri Feb 17 19:23:19 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -51,6 +51,10 @@ signal sysc_gpcr_fmc_scl_dly0 : std_logic ;
signal sysc_gpcr_fmc_scl_int : std_logic ;
signal sysc_gpcr_fmc_sda_dly0 : std_logic ;
signal sysc_gpcr_fmc_sda_int : std_logic ;
signal sysc_gpcr_sfp_scl_dly0 : std_logic ;
signal sysc_gpcr_sfp_scl_int : std_logic ;
signal sysc_gpcr_sfp_sda_dly0 : std_logic ;
signal sysc_gpcr_sfp_sda_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
......@@ -88,10 +92,14 @@ begin
regs_o.gpsr_fmc_scl_load_o <= '0';
regs_o.gpsr_fmc_sda_load_o <= '0';
sysc_gpsr_net_rst_int <= '0';
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
sysc_gpcr_fmc_sda_int <= '0';
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
sysc_tcr_enable_int <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
......@@ -105,15 +113,21 @@ begin
regs_o.gpsr_fmc_scl_load_o <= '0';
regs_o.gpsr_fmc_sda_load_o <= '0';
sysc_gpsr_net_rst_int <= '0';
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
sysc_gpcr_fmc_sda_int <= '0';
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
ack_in_progress <= '0';
else
regs_o.rstr_trig_wr_o <= '0';
regs_o.gpsr_fmc_scl_load_o <= '0';
regs_o.gpsr_fmc_sda_load_o <= '0';
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -173,6 +187,11 @@ begin
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
regs_o.gpsr_sfp_scl_load_o <= '1';
rddata_reg(9) <= 'X';
regs_o.gpsr_sfp_sda_load_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -181,9 +200,9 @@ begin
rddata_reg(4) <= 'X';
rddata_reg(5) <= regs_i.gpsr_btn1_i;
rddata_reg(6) <= regs_i.gpsr_btn2_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -219,11 +238,17 @@ begin
rddata_reg(2) <= 'X';
sysc_gpcr_fmc_sda_int <= wrdata_reg(3);
rddata_reg(3) <= 'X';
sysc_gpcr_sfp_scl_int <= wrdata_reg(8);
rddata_reg(8) <= 'X';
sysc_gpcr_sfp_sda_int <= wrdata_reg(9);
rddata_reg(9) <= 'X';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -393,6 +418,11 @@ begin
-- SPEC Pushbutton 1 state
-- SPEC Pushbutton 2 state
-- SFP detect (MOD_DEF0 signal)
-- SFP I2C bitbanged SCL
regs_o.gpsr_sfp_scl_o <= wrdata_reg(8);
-- SFP I2C bitbanged SDA
regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
-- Status LED
process (bus_clock_int, rst_n_i)
begin
......@@ -445,6 +475,32 @@ begin
end process;
-- SFP I2C bitbanged SCL
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_sfp_scl_dly0 <= '0';
regs_o.gpcr_sfp_scl_o <= '0';
elsif rising_edge(bus_clock_int) then
sysc_gpcr_sfp_scl_dly0 <= sysc_gpcr_sfp_scl_int;
regs_o.gpcr_sfp_scl_o <= sysc_gpcr_sfp_scl_int and (not sysc_gpcr_sfp_scl_dly0);
end if;
end process;
-- FMC I2C bitbanged SDA
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_sfp_sda_dly0 <= '0';
regs_o.gpcr_sfp_sda_o <= '0';
elsif rising_edge(bus_clock_int) then
sysc_gpcr_sfp_sda_dly0 <= sysc_gpcr_sfp_sda_int;
regs_o.gpcr_sfp_sda_o <= sysc_gpcr_sfp_sda_int and (not sysc_gpcr_sfp_sda_dly0);
end if;
end process;
-- Memory size
-- Timer Divider
-- Timer Enable
......
modules/wrc_core/wrc_syscon_wb.wb
+ 51
− 0
View file @ 503fd2cc
......@@ -94,6 +94,40 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SFP detect (MOD_DEF0 signal)";
prefix = "sfp_det";
description = "read : returns the state of the SFP's MOD_DEF0 line";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SFP I2C bitbanged SCL";
prefix = "sfp_scl";
description = "write 1: Set SFP SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 8;
};
field {
name = "SFP I2C bitbanged SDA";
prefix = "sfp_sda";
description = "write 1: Set SFP SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 9;
};
};
reg {
......@@ -129,6 +163,23 @@ peripheral {
read : returns the current status of the SCL line.";
type = MONOSTABLE;
};
field {
name = "SFP I2C bitbanged SCL";
prefix = "sfp_scl";
description = "write 1: Set SFP SCL line to 0.";
type = MONOSTABLE;
align = 8;
};
field {
name = "FMC I2C bitbanged SDA";
prefix = "sfp_sda";
description = "write 1: Set SFP SDA line to 0.";
type = MONOSTABLE;
align = 9;
};
};
reg {
......
modules/wrc_core/wrcore_pkg.vhd
+ 5
− 0
View file @ 503fd2cc
......@@ -106,6 +106,11 @@ package wrcore_pkg is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
memsize_i : in std_logic_vector(3 downto 0);
btn1_i : in std_logic;
btn2_i : in std_logic;
......
modules/wrc_core/xwr_core.vhd
+ 15
− 0
View file @ 503fd2cc
......@@ -104,6 +104,11 @@ entity xwr_core is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
......@@ -207,6 +212,11 @@ architecture struct of xwr_core is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
......@@ -311,6 +321,11 @@ begin
scl_i => scl_i,
sda_o => sda_o,
sda_i => sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
btn1_i => btn1_i,
btn2_i => btn2_i,
uart_rxd_i => uart_rxd_i,
......
sim/wrc_syscon_regs.vh
+ 14
− 2
View file @ 503fd2cc
`define ADDR_SYSC_RSTR 5'h0
`define SYSC_RSTR_HRST_OFFSET 0
`define SYSC_RSTR_HRST 32'hffffffff
`define SYSC_RSTR_TRIG_OFFSET 0
`define SYSC_RSTR_TRIG 32'h0fffffff
`define SYSC_RSTR_RST_OFFSET 28
`define SYSC_RSTR_RST 32'h10000000
`define ADDR_SYSC_GPSR 5'h4
`define SYSC_GPSR_LED_STAT_OFFSET 0
`define SYSC_GPSR_LED_STAT 32'h00000001
......@@ -16,6 +18,12 @@
`define SYSC_GPSR_BTN1 32'h00000020
`define SYSC_GPSR_BTN2_OFFSET 6
`define SYSC_GPSR_BTN2 32'h00000040
`define SYSC_GPSR_SFP_DET_OFFSET 7
`define SYSC_GPSR_SFP_DET 32'h00000080
`define SYSC_GPSR_SFP_SCL_OFFSET 8
`define SYSC_GPSR_SFP_SCL 32'h00000100
`define SYSC_GPSR_SFP_SDA_OFFSET 9
`define SYSC_GPSR_SFP_SDA 32'h00000200
`define ADDR_SYSC_GPCR 5'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
......@@ -25,6 +33,10 @@
`define SYSC_GPCR_FMC_SCL 32'h00000004
`define SYSC_GPCR_FMC_SDA_OFFSET 3
`define SYSC_GPCR_FMC_SDA 32'h00000008
`define SYSC_GPCR_SFP_SCL_OFFSET 8
`define SYSC_GPCR_SFP_SCL 32'h00000100
`define SYSC_GPCR_SFP_SDA_OFFSET 9
`define SYSC_GPCR_SFP_SDA 32'h00000200
`define ADDR_SYSC_HWFR 5'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
......
top/spec_1_1/wr_core_demo/spec_top.ucf
+ 3
− 3
View file @ 503fd2cc
......@@ -37,7 +37,7 @@ NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = F17;
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
......@@ -47,7 +47,7 @@ NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = C17;
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
......@@ -629,4 +629,4 @@ NET "U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
top/spec_1_1/wr_core_demo/spec_top.vhd
+ 24
− 9
View file @ 503fd2cc
......@@ -92,7 +92,7 @@ entity spec_top is
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_b : inout std_logic; -- rate_select
sfp_mod_def0_b : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
......@@ -268,6 +268,11 @@ architecture rtl of spec_top is
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
......@@ -441,6 +446,10 @@ architecture rtl of spec_top is
signal wrc_scl_i : std_logic;
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
signal sfp_scl_o : std_logic;
signal sfp_scl_i : std_logic;
signal sfp_sda_o : std_logic;
signal sfp_sda_i : std_logic;
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
......@@ -741,6 +750,11 @@ begin
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z';
sfp_scl_i <= sfp_mod_def1_b;
sfp_sda_i <= sfp_mod_def2_b;
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
......@@ -778,10 +792,15 @@ begin
led_red_o => LED_RED,
led_green_o => LED_GREEN,
scl_o => wrc_scl_o, --fpga_scl_b,
scl_i => wrc_scl_i, --fpga_scl_b,
sda_o => wrc_sda_o, --fpga_sda_b,
sda_i => wrc_sda_i, --fpga_sda_b,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b,
btn1_i => button1_i,
btn2_i => button2_i,
......@@ -966,10 +985,6 @@ begin
dio_sdn_ck_n_o <= '1';
dio_sdn_n_o <= '1';
sfp_mod_def0_b <= '0';
sfp_mod_def1_b <= '0';
sfp_mod_def2_b <= '0';
sfp_tx_disable_o <= '0';
--chipscope_ila_1 : chipscope_ila
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment