This had nothing to do with WR, wasn't used here, and is now removed.

Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago

This may fix the WRs locking offsets issue & save a lot of FPGA resources.

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

also, the datasheet says our new flash chips are only good to 33MHz
with slow reads. change quartus fpga load config to 20MHz (not 40).

bugfixes

When WR starts up on a node, the first thing it does is kill its link.
Previously on Altera we ignored attempts to reset the link and thus
the switch never sees the link go down. It seems this matters.

The autonegotiation state machine uses an_rx_val in the sys clock domain.
The rx pcs passes the an_rx_val to the sys domain using a handshake.
Unfortunately, the value can change even after the handshake goes high.
On Altera, this led to the autonegotiation state machine entering state "0".
... from which it would never leave and the link stayed dead forever.

On Altera platforms this bug manifests as the minic failing to TX packets
correctly and the whole PTP state machine grinding to a halt.

This was already fixed in the 16bit version.

Tomasz Wlostowski authored 12 years ago and Grzegorz Daniluk committed 12 years ago

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Previously on Altera, there was a non-deterministic delay between
transmission from clk_ref to clk_tx. This came from a FIFO in the
GXB and also that clk_tx was not compensated against clk_ref.

Using deterministic mode with PFD feedback achieves determinism.
There is only a single register instead of the FIFO and the parallel
TX clock is phase matched to the CMU reference clock.

Unfortunately, deterministic mode does not have access to force_dispval.
This necessitates using an 8b10b in the FPGA fabric.

Another change is that the CDR clock is trained by a GXB reference
clock pin for better jitter performance. It is forbidden to cascade
two PLLs in low bandwidth mode. This way the recovered clock can use
low bandwidth as it is never derived from clk_ref (also low bandwidth).

Another change is the reset logic has been rewired. Before the WRC
could reset the GXB and thus kill the RX clock. This led to bad
undefined states in the RX state machiens. Now reset as in the manual.

This was a (faulty) prototype card produced in limited number.
It will be replaced by an entirely new design using Arria5.

This project completely out-of-date compared to the other GSI tops.
When the new card is built, we will just make a completely new top.

After transmitting a frame in software, the LM32 reads out the
timestamp set by hardware. Naturally, this comes after the frame
has been sent, so the LM32 must wait.

Prior to this patch the only thing it could wait for was DMA idle.
However, DMA of the packet completes before the timestamp is ready.
Thus there was a race condition where the LM32 would see an old TS.

Conflicts:
	modules/wr_tlu/wb_timestamp_latch.vhd