wr_gtx_phy_virtex6_lp: reduce phy calibration only to first 12 ports of wrs

platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd

@@ -258,7 +258,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
   signal tx_data_swapped : std_logic_vector(15 downto 0);
 
   signal cur_disp                               : t_8b10b_disparity;
-  signal tx_out_clk                             : std_logic;
+  signal tx_out_clk, tx_out_clk_buf             : std_logic;
   signal rx_rec_clk_sampled, tx_out_clk_sampled : std_logic;
 
   signal tx_rundisp_v6  : std_logic_vector(1 downto 0);
@@ -328,13 +328,17 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
 
   end generate gen_bufr_for_tx_clock;
 
-  gen_bufg_for_tx_clock :  if not g_use_bufr_for_tx_clock generate
+  gen_bufg_for_tx_clock :  if not g_use_bufr_for_tx_clock and g_id < 12 generate
   BUFG_1 : BUFG
     port map (
       O => tx_out_clk,
       I => tx_out_clk_buf);
 
   end generate gen_bufg_for_tx_clock;
+
+  gen_no_tx_clock : if g_id > 11 generate
+    tx_out_clk <= '0';
+  end generate;
   
 
   U_Sampler_RX : dmtd_sampler
@@ -468,7 +472,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
       TXCHARISK_IN        => tx_is_k_swapped,
       GTXTEST_IN          => gtx_test,
       TXDATA_IN           => tx_data_swapped,
-      TXOUTCLK_OUT        => tx_out_clk,
+      TXOUTCLK_OUT        => tx_out_clk_buf,
       TXUSRCLK2_IN        => clk_ref_i,
       TXRUNDISP_OUT       => open,
       TXN_OUT             => pad_txn_o,