From 5dd8a5a096b85b51439bcebfafb45cfb94922b52 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Wed, 10 Jul 2019 08:35:36 +0200
Subject: [PATCH] wr_gtx_phy_virtex6_lp: reduce phy calibration only to first
12 ports of wrs
---
.../virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd b/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
index 162ca925..955b9efa 100644
--- a/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
+++ b/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
@@ -258,7 +258,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
- signal tx_out_clk : std_logic;
+ signal tx_out_clk, tx_out_clk_buf : std_logic;
signal rx_rec_clk_sampled, tx_out_clk_sampled : std_logic;
signal tx_rundisp_v6 : std_logic_vector(1 downto 0);
@@ -328,13 +328,17 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
end generate gen_bufr_for_tx_clock;
- gen_bufg_for_tx_clock : if not g_use_bufr_for_tx_clock generate
+ gen_bufg_for_tx_clock : if not g_use_bufr_for_tx_clock and g_id < 12 generate
BUFG_1 : BUFG
port map (
O => tx_out_clk,
I => tx_out_clk_buf);
end generate gen_bufg_for_tx_clock;
+
+ gen_no_tx_clock : if g_id > 11 generate
+ tx_out_clk <= '0';
+ end generate;
U_Sampler_RX : dmtd_sampler
@@ -468,7 +472,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
TXCHARISK_IN => tx_is_k_swapped,
GTXTEST_IN => gtx_test,
TXDATA_IN => tx_data_swapped,
- TXOUTCLK_OUT => tx_out_clk,
+ TXOUTCLK_OUT => tx_out_clk_buf,
TXUSRCLK2_IN => clk_ref_i,
TXRUNDISP_OUT => open,
TXN_OUT => pad_txn_o,
--
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