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Commit 2b48f677 authored by Maciej Lipinski's avatar Maciej Lipinski
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[board/vfchd] updated vfchd board to allow connection of user-defined aux_diag

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board/vfchd/wr_vfchd_pkg.vhd
+ 14
− 2
View file @ 2b48f677
......@@ -15,7 +15,11 @@ package wr_vfchd_pkg is
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port (
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
......@@ -66,6 +70,8 @@ package wr_vfchd_pkg is
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
led_act_o : out std_logic);
end component xwrc_board_vfchd;
......@@ -76,7 +82,11 @@ package wr_vfchd_pkg is
g_pcs_16bit : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0);
port (
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
......@@ -163,6 +173,8 @@ package wr_vfchd_pkg is
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
led_act_o : out std_logic);
end component wrc_board_vfchd;
......
board/vfchd/wrc_board_vfchd.vhd
+ 32
− 2
View file @ 2b48f677
......@@ -68,7 +68,13 @@ entity wrc_board_vfchd is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif"
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
);
port (
---------------------------------------------------------------------------
......@@ -212,6 +218,13 @@ entity wrc_board_vfchd is
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- WRPC timing interface and status
---------------------------------------------------------------------------
......@@ -247,6 +260,13 @@ architecture std_wrapper of wrc_board_vfchd is
signal wb_eth_master_out : t_wishbone_master_out;
signal wb_eth_master_in : t_wishbone_master_in;
-- Aux diagnostics
constant c_diag_ro_size : integer:= g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer:= g_diag_rw_vector_width/32;
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
begin -- architecture struct
-- Map top-level signals to internal records
......@@ -301,6 +321,10 @@ begin -- architecture struct
wb_eth_master_in.rty <= wb_eth_rty_i;
wb_eth_master_in.stall <= wb_eth_stall_i;
-- auxiliary diagnostics
aux_diag_in <= f_de_vectorize_diag(aux_diag_i,g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
-- Instantiate the records-based module
cmp_xwrc_board_vfchd : xwrc_board_vfchd
generic map (
......@@ -309,7 +333,11 @@ begin -- architecture struct
g_pcs_16bit => f_int2bool(g_pcs_16bit),
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamer_width => g_streamer_width,
g_dpram_initf => g_dpram_initf)
g_dpram_initf => g_dpram_initf,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size)
port map (
clk_board_125m_i => clk_board_125m_i,
clk_board_20m_i => clk_board_20m_i,
......@@ -359,6 +387,8 @@ begin -- architecture struct
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_link_o => led_link_o,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
led_act_o => led_act_o);
end architecture std_wrapper;
board/vfchd/xwrc_board_vfchd.vhd
+ 20
− 5
View file @ 2b48f677
......@@ -66,7 +66,13 @@ entity xwrc_board_vfchd is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif"
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port (
---------------------------------------------------------------------------
......@@ -174,6 +180,13 @@ entity xwrc_board_vfchd is
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- WRPC timing interface and status
---------------------------------------------------------------------------
......@@ -369,10 +382,10 @@ begin -- architecture struct
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => g_pcs_16bit,
g_diag_id => 0,
g_diag_ver => 0,
g_diag_ro_size => c_WR_TRANS_ARR_SIZE_OUT,
g_diag_rw_size => c_WR_TRANS_ARR_SIZE_IN,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamer_width => g_streamer_width,
g_fabric_iface => g_fabric_iface
)
......@@ -451,6 +464,8 @@ begin -- architecture struct
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
link_ok_o => open);
end architecture struct;
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