[board/svec] trivial bugfix: was missing std_logic declaration of input port

board/svec/wrc_board_svec.vhd

@@ -243,7 +243,7 @@ entity wrc_board_svec is
     -- WRPC timing interface and status
     ---------------------------------------------------------------------------
 
-    pps_ext_i       : in                                                     := '0';
+    pps_ext_i       : in  std_logic                                         := '0';
     pps_p_o         : out std_logic;
     pps_led_o       : out std_logic;
     tm_time_valid_o : out std_logic;