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Commit 0aa2310d authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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Endpoint-PAUSE: changing naming of 802.3 pause in WB regs so that it's compatible with old versions

parent 2605d988
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modules/wr_endpoint/ep_registers_pkg.vhd
+ 4
− 4
View file @ 0aa2310d
......@@ -91,8 +91,8 @@ package ep_wbgen2_pkg is
pfcr1_mm_data_lsb_wr_o : std_logic;
tcar_pcp_map_o : std_logic_vector(23 downto 0);
tcar_pcp_map_load_o : std_logic;
fcr_rxpause_802_3_o : std_logic;
fcr_txpause_802_3_o : std_logic;
fcr_rxpause_o : std_logic;
fcr_txpause_o : std_logic;
fcr_rxpause_802_1q_o : std_logic;
fcr_txpause_802_1q_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
......@@ -148,8 +148,8 @@ package ep_wbgen2_pkg is
pfcr1_mm_data_lsb_wr_o => '0',
tcar_pcp_map_o => (others => '0'),
tcar_pcp_map_load_o => '0',
fcr_rxpause_802_3_o => '0',
fcr_txpause_802_3_o => '0',
fcr_rxpause_o => '0',
fcr_txpause_o => '0',
fcr_rxpause_802_1q_o => '0',
fcr_txpause_802_1q_o => '0',
fcr_tx_thr_o => (others => '0'),
......
modules/wr_endpoint/ep_rx_early_address_match.vhd
+ 1
− 1
View file @ 0aa2310d
......@@ -131,7 +131,7 @@ begin -- behavioral
match_is_pause <= '1'; -- to indicate that frame shall be dropped
if(regs_i.fcr_rxpause_802_3_o = '1') then
if(regs_i.fcr_rxpause_o = '1') then
match_pause_req <= '1';
match_pause_quanta <= snk_fab_i.data;
pause_prio_mask <= (others => '1');
......
modules/wr_endpoint/ep_wishbone_controller.vhd
+ 11
− 11
View file @ 0aa2310d
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Tue Mar 12 12:27:15 2013
-- Created : Tue Mar 12 16:46:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -69,8 +69,8 @@ signal ep_vcr0_fix_prio_int : std_logic ;
signal ep_vcr0_prio_val_int : std_logic_vector(2 downto 0);
signal ep_vcr0_pvid_int : std_logic_vector(11 downto 0);
signal ep_pfcr0_enable_int : std_logic ;
signal ep_fcr_rxpause_802_3_int : std_logic ;
signal ep_fcr_txpause_802_3_int : std_logic ;
signal ep_fcr_rxpause_int : std_logic ;
signal ep_fcr_txpause_int : std_logic ;
signal ep_fcr_rxpause_802_1q_int : std_logic ;
signal ep_fcr_txpause_802_1q_int : std_logic ;
signal ep_fcr_tx_thr_int : std_logic_vector(7 downto 0);
......@@ -135,8 +135,8 @@ begin
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
regs_o.tcar_pcp_map_load_o <= '0';
ep_fcr_rxpause_802_3_int <= '0';
ep_fcr_txpause_802_3_int <= '0';
ep_fcr_rxpause_int <= '0';
ep_fcr_txpause_int <= '0';
ep_fcr_rxpause_802_1q_int <= '0';
ep_fcr_txpause_802_1q_int <= '0';
ep_fcr_tx_thr_int <= "00000000";
......@@ -457,15 +457,15 @@ begin
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
ep_fcr_rxpause_802_3_int <= wrdata_reg(0);
ep_fcr_txpause_802_3_int <= wrdata_reg(1);
ep_fcr_rxpause_int <= wrdata_reg(0);
ep_fcr_txpause_int <= wrdata_reg(1);
ep_fcr_rxpause_802_1q_int <= wrdata_reg(2);
ep_fcr_txpause_802_1q_int <= wrdata_reg(3);
ep_fcr_tx_thr_int <= wrdata_reg(15 downto 8);
ep_fcr_tx_quanta_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(0) <= ep_fcr_rxpause_802_3_int;
rddata_reg(1) <= ep_fcr_txpause_802_3_int;
rddata_reg(0) <= ep_fcr_rxpause_int;
rddata_reg(1) <= ep_fcr_txpause_int;
rddata_reg(2) <= ep_fcr_rxpause_802_1q_int;
rddata_reg(3) <= ep_fcr_txpause_802_1q_int;
rddata_reg(15 downto 8) <= ep_fcr_tx_thr_int;
......@@ -774,9 +774,9 @@ begin
-- 802.1Q priority tag to Traffic Class map
regs_o.tcar_pcp_map_o <= wrdata_reg(23 downto 0);
-- RX Pause 802.3 enable
regs_o.fcr_rxpause_802_3_o <= ep_fcr_rxpause_802_3_int;
regs_o.fcr_rxpause_o <= ep_fcr_rxpause_int;
-- TX Pause 802.3 enable
regs_o.fcr_txpause_802_3_o <= ep_fcr_txpause_802_3_int;
regs_o.fcr_txpause_o <= ep_fcr_txpause_int;
-- Rx Pause 802.1Q enable
regs_o.fcr_rxpause_802_1q_o <= ep_fcr_rxpause_802_1q_int;
-- Tx Pause 802.1Q enable (not implemented)
......
modules/wr_endpoint/ep_wishbone_controller.wb
+ 2
− 2
View file @ 0aa2310d
......@@ -425,7 +425,7 @@ peripheral {
name = "RX Pause 802.3 enable";
description = "1: enable reception of pause frames defined in 802.3 (all priorities) and TX path throttling \
0: disable reception of pause frames defined in 802.3";
prefix = "RXPAUSE_802_3";
prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
......@@ -434,7 +434,7 @@ peripheral {
name = "TX Pause 802.3 enable";
description = "1: enable transmission of pause frames and RX path throttling \
0: disable transmission of pause frames";
prefix = "TXPAUSE_802_3";
prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
......
sim/endpoint_regs.v
+ 4
− 4
View file @ 0aa2310d
......@@ -67,10 +67,10 @@
`define EP_TCAR_PCP_MAP_OFFSET 0
`define EP_TCAR_PCP_MAP 32'h00ffffff
`define ADDR_EP_FCR 7'h20
`define EP_FCR_RXPAUSE_802_3_OFFSET 0
`define EP_FCR_RXPAUSE_802_3 32'h00000001
`define EP_FCR_TXPAUSE_802_3_OFFSET 1
`define EP_FCR_TXPAUSE_802_3 32'h00000002
`define EP_FCR_RXPAUSE_OFFSET 0
`define EP_FCR_RXPAUSE 32'h00000001
`define EP_FCR_TXPAUSE_OFFSET 1
`define EP_FCR_TXPAUSE 32'h00000002
`define EP_FCR_RXPAUSE_802_1Q_OFFSET 2
`define EP_FCR_RXPAUSE_802_1Q 32'h00000004
`define EP_FCR_TXPAUSE_802_1Q_OFFSET 3
......
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