diff --git a/modules/wr_endpoint/ep_registers_pkg.vhd b/modules/wr_endpoint/ep_registers_pkg.vhd
index 97e00b8959aa038e0f502d75ba1383137a340990..a682f01e0e0e8fcf6afec16a3170c8e0bc318920 100644
--- a/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -91,8 +91,8 @@ package ep_wbgen2_pkg is
pfcr1_mm_data_lsb_wr_o : std_logic;
tcar_pcp_map_o : std_logic_vector(23 downto 0);
tcar_pcp_map_load_o : std_logic;
- fcr_rxpause_802_3_o : std_logic;
- fcr_txpause_802_3_o : std_logic;
+ fcr_rxpause_o : std_logic;
+ fcr_txpause_o : std_logic;
fcr_rxpause_802_1q_o : std_logic;
fcr_txpause_802_1q_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
@@ -148,8 +148,8 @@ package ep_wbgen2_pkg is
pfcr1_mm_data_lsb_wr_o => '0',
tcar_pcp_map_o => (others => '0'),
tcar_pcp_map_load_o => '0',
- fcr_rxpause_802_3_o => '0',
- fcr_txpause_802_3_o => '0',
+ fcr_rxpause_o => '0',
+ fcr_txpause_o => '0',
fcr_rxpause_802_1q_o => '0',
fcr_txpause_802_1q_o => '0',
fcr_tx_thr_o => (others => '0'),
diff --git a/modules/wr_endpoint/ep_rx_early_address_match.vhd b/modules/wr_endpoint/ep_rx_early_address_match.vhd
index f17f356344aa0bc8e8f71183fcdd9eed6b90cf6c..407298e648ace66c97e618cd64c3d0201f2bc5d1 100644
--- a/modules/wr_endpoint/ep_rx_early_address_match.vhd
+++ b/modules/wr_endpoint/ep_rx_early_address_match.vhd
@@ -131,7 +131,7 @@ begin -- behavioral
match_is_pause <= '1'; -- to indicate that frame shall be dropped
- if(regs_i.fcr_rxpause_802_3_o = '1') then
+ if(regs_i.fcr_rxpause_o = '1') then
match_pause_req <= '1';
match_pause_quanta <= snk_fab_i.data;
pause_prio_mask <= (others => '1');
diff --git a/modules/wr_endpoint/ep_wishbone_controller.vhd b/modules/wr_endpoint/ep_wishbone_controller.vhd
index defae7100d62ac700c94a94084c7d8275f0e0a8b..59d785896f9159bfe1916b006707bc6493c5244b 100644
--- a/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/modules/wr_endpoint/ep_wishbone_controller.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
--- Created : Tue Mar 12 12:27:15 2013
+-- Created : Tue Mar 12 16:46:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
@@ -69,8 +69,8 @@ signal ep_vcr0_fix_prio_int : std_logic ;
signal ep_vcr0_prio_val_int : std_logic_vector(2 downto 0);
signal ep_vcr0_pvid_int : std_logic_vector(11 downto 0);
signal ep_pfcr0_enable_int : std_logic ;
-signal ep_fcr_rxpause_802_3_int : std_logic ;
-signal ep_fcr_txpause_802_3_int : std_logic ;
+signal ep_fcr_rxpause_int : std_logic ;
+signal ep_fcr_txpause_int : std_logic ;
signal ep_fcr_rxpause_802_1q_int : std_logic ;
signal ep_fcr_txpause_802_1q_int : std_logic ;
signal ep_fcr_tx_thr_int : std_logic_vector(7 downto 0);
@@ -135,8 +135,8 @@ begin
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.pfcr1_mm_data_lsb_wr_o <= '0';
regs_o.tcar_pcp_map_load_o <= '0';
- ep_fcr_rxpause_802_3_int <= '0';
- ep_fcr_txpause_802_3_int <= '0';
+ ep_fcr_rxpause_int <= '0';
+ ep_fcr_txpause_int <= '0';
ep_fcr_rxpause_802_1q_int <= '0';
ep_fcr_txpause_802_1q_int <= '0';
ep_fcr_tx_thr_int <= "00000000";
@@ -457,15 +457,15 @@ begin
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
- ep_fcr_rxpause_802_3_int <= wrdata_reg(0);
- ep_fcr_txpause_802_3_int <= wrdata_reg(1);
+ ep_fcr_rxpause_int <= wrdata_reg(0);
+ ep_fcr_txpause_int <= wrdata_reg(1);
ep_fcr_rxpause_802_1q_int <= wrdata_reg(2);
ep_fcr_txpause_802_1q_int <= wrdata_reg(3);
ep_fcr_tx_thr_int <= wrdata_reg(15 downto 8);
ep_fcr_tx_quanta_int <= wrdata_reg(31 downto 16);
end if;
- rddata_reg(0) <= ep_fcr_rxpause_802_3_int;
- rddata_reg(1) <= ep_fcr_txpause_802_3_int;
+ rddata_reg(0) <= ep_fcr_rxpause_int;
+ rddata_reg(1) <= ep_fcr_txpause_int;
rddata_reg(2) <= ep_fcr_rxpause_802_1q_int;
rddata_reg(3) <= ep_fcr_txpause_802_1q_int;
rddata_reg(15 downto 8) <= ep_fcr_tx_thr_int;
@@ -774,9 +774,9 @@ begin
-- 802.1Q priority tag to Traffic Class map
regs_o.tcar_pcp_map_o <= wrdata_reg(23 downto 0);
-- RX Pause 802.3 enable
- regs_o.fcr_rxpause_802_3_o <= ep_fcr_rxpause_802_3_int;
+ regs_o.fcr_rxpause_o <= ep_fcr_rxpause_int;
-- TX Pause 802.3 enable
- regs_o.fcr_txpause_802_3_o <= ep_fcr_txpause_802_3_int;
+ regs_o.fcr_txpause_o <= ep_fcr_txpause_int;
-- Rx Pause 802.1Q enable
regs_o.fcr_rxpause_802_1q_o <= ep_fcr_rxpause_802_1q_int;
-- Tx Pause 802.1Q enable (not implemented)
diff --git a/modules/wr_endpoint/ep_wishbone_controller.wb b/modules/wr_endpoint/ep_wishbone_controller.wb
index 2723bfc15eedaa3cca98351018ac0785a5979d39..2e601a12a48df03a67fe0eb37dc72a47f2a503f2 100644
--- a/modules/wr_endpoint/ep_wishbone_controller.wb
+++ b/modules/wr_endpoint/ep_wishbone_controller.wb
@@ -425,7 +425,7 @@ peripheral {
name = "RX Pause 802.3 enable";
description = "1: enable reception of pause frames defined in 802.3 (all priorities) and TX path throttling \
0: disable reception of pause frames defined in 802.3";
- prefix = "RXPAUSE_802_3";
+ prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
@@ -434,7 +434,7 @@ peripheral {
name = "TX Pause 802.3 enable";
description = "1: enable transmission of pause frames and RX path throttling \
0: disable transmission of pause frames";
- prefix = "TXPAUSE_802_3";
+ prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
diff --git a/sim/endpoint_regs.v b/sim/endpoint_regs.v
index 1e81af53ccded08d90f95528502767b3ec97e8c6..4501235a49059f6ce7028690ae00e404cef376ab 100644
--- a/sim/endpoint_regs.v
+++ b/sim/endpoint_regs.v
@@ -67,10 +67,10 @@
`define EP_TCAR_PCP_MAP_OFFSET 0
`define EP_TCAR_PCP_MAP 32'h00ffffff
`define ADDR_EP_FCR 7'h20
-`define EP_FCR_RXPAUSE_802_3_OFFSET 0
-`define EP_FCR_RXPAUSE_802_3 32'h00000001
-`define EP_FCR_TXPAUSE_802_3_OFFSET 1
-`define EP_FCR_TXPAUSE_802_3 32'h00000002
+`define EP_FCR_RXPAUSE_OFFSET 0
+`define EP_FCR_RXPAUSE 32'h00000001
+`define EP_FCR_TXPAUSE_OFFSET 1
+`define EP_FCR_TXPAUSE 32'h00000002
`define EP_FCR_RXPAUSE_802_1Q_OFFSET 2
`define EP_FCR_RXPAUSE_802_1Q 32'h00000004
`define EP_FCR_TXPAUSE_802_1Q_OFFSET 3