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Virtex5_PHY_fix
724f4a88
·
[Virtex5 PHY] drive rdy_o and cleanup
·
Dec 10, 2020
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ML-tmp-debug-btrain
f8399d53
·
make simulation work
·
Jan 08, 2021
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ML-tmp-btrain-debug-v6
354b935f
·
dirty hack to make simulation work
·
Jan 08, 2021
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pascal_spidr4
6c060087
·
removed ps_uart
·
Jan 12, 2021
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jgarcia-spec7-ddr-pl
886d0b8a
·
Support the DDR3 at PL as a PS and XDMA AXI peripheral for test purposes
·
Mar 08, 2021
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jgarcia-spec7-ddr-pl-256-bit
6c434a4c
·
Support the DDR3 at PL as an XDMA AXI high-bandwidth peripheral for test purposes
·
Mar 10, 2021
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tom-wrpc-riscv-for-adam-feb19
37c92c65
·
trivial testbench for the PRBS checker
·
Apr 14, 2021
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tom-prbs-check-apr14
9d1f991f
·
wr_gthe4_phy_family7: add optional system IBERT
·
Apr 15, 2021
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peter_210422_align10mhz
25f431c5
·
remove aligned_10mhz_o and restore PPS on Spare BullsEye
·
Apr 22, 2021
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diot-sb
6e64fab1
·
adding top project for DI/OT System Board
·
May 07, 2021
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spec_v5_with_62m5_dio_ouput
3b347340
·
replace dio(1) with 62.5 MHz out clock
·
Sep 07, 2021
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gsi_master_get_back_on_track_2022
fc654127
·
altera: added PHY Manifest.py (scu4)
·
Sep 15, 2021
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tom-wrpc-v5-oversampled-ddmtd
52a19ff9
·
top/spec_ref_design: si57x disciplining demo @ 100 MHz
·
Oct 15, 2021
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spec7_master
7655749b
·
Add GTH selection for Artix UltraScale+ AU10, AU15
·
Dec 09, 2021
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peter_211210_GTHe4_TXOUTCLK_Bug
6d93f15c
·
Is this a gthe4 wizzard bug?
·
Dec 10, 2021
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gsi_master_get_back_on_track
48f04c06
·
ftm4: added phy stuff
·
Feb 11, 2022
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ci-test
26d2d7ae
·
testing new CI by Kostas
·
Feb 15, 2022
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wrpc-v5-lm32
d7453e86
·
board/common: re-allow streamer and etherbone
·
Mar 28, 2022
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fmc-adc-bufg
3884a655
·
xwrc_platform_xilinx.vhd: remove bufg before plls
·
Mar 31, 2022
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esrf-whist_wrpc-v4.2
5999b631
·
add clock output from wr pll for FLASH interface (xil_multiboot module).
·
May 25, 2022
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