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spec_v5_with_62m5_dio_ouput
3b347340
·
replace dio(1) with 62.5 MHz out clock
·
Sep 07, 2021
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diot-sb
6e64fab1
·
adding top project for DI/OT System Board
·
May 07, 2021
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peter_210422_align10mhz
25f431c5
·
remove aligned_10mhz_o and restore PPS on Spare BullsEye
·
Apr 22, 2021
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tom-prbs-check-apr14
9d1f991f
·
wr_gthe4_phy_family7: add optional system IBERT
·
Apr 15, 2021
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tom-wrpc-riscv-for-adam-feb19
37c92c65
·
trivial testbench for the PRBS checker
·
Apr 14, 2021
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jgarcia-spec7-ddr-pl-256-bit
6c434a4c
·
Support the DDR3 at PL as an XDMA AXI high-bandwidth peripheral for test purposes
·
Mar 10, 2021
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jgarcia-spec7-ddr-pl
886d0b8a
·
Support the DDR3 at PL as a PS and XDMA AXI peripheral for test purposes
·
Mar 08, 2021
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pascal_spidr4
6c060087
·
removed ps_uart
·
Jan 12, 2021
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ML-tmp-btrain-debug-v6
354b935f
·
dirty hack to make simulation work
·
Jan 08, 2021
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ML-tmp-debug-btrain
f8399d53
·
make simulation work
·
Jan 08, 2021
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Virtex5_PHY_fix
724f4a88
·
[Virtex5 PHY] drive rdy_o and cleanup
·
Dec 10, 2020
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tom-dec07
bf13e6b9
·
virtex5: bypass internal PHY 8b10b decoder + improved alignment detect/reset
·
Dec 07, 2020
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ML-tmp-virtex5_phy_resets
8fa73b6e
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[PHY/Virtex5] synchronize resets with rx_clk
·
Dec 05, 2020
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greg-256k
2915154b
·
more LM32 memory for software development
·
Nov 13, 2020
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adam-192k
69b9be7f
·
more LM32 memory for software development
·
Nov 13, 2020
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tom-nov06
d5952890
·
platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3
·
Nov 06, 2020
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tom-nov02
7771d098
·
wr_core: added generic to select LM32 RAM address space size (128/256 kB). Default = 128 kB
·
Nov 02, 2020
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gsi_master_get_back_on_track_oct2020_softpll_fix
7fc7954a
·
wr_core/softpll_ng: fixed irq bug
·
Oct 26, 2020
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tom-svec7
112099e2
·
wr_gtx_phy_family7: made clock buffers optional through generic
·
Oct 02, 2020
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peter_spec7_v5
276cf6db
·
Repaired wrc_core memory map comment (due to Toms commit
3e433e26
"wrc_core:...
·
Sep 22, 2020
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