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tom-sis83k-jul17
8723297f
·
platform/xilinx: revert to Vivado-generated wrapper for GTHE3
·
Jul 17, 2020
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tom-may13
db907e76
·
wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counter
·
Jul 03, 2020
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tom-proposed-master-jun30
f2e9c962
·
wr_gthe3_phy_family7: possible fix for failing link up detection after disconnecting the fiber
·
Jul 01, 2020
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tom-afcz-jun26
d96c66c2
·
wr_gthe4_phy_family7: fix RX CDR lock & clocking for AFCZ
·
Jun 26, 2020
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guidov_hpsec
7f6ca9ce
·
Some notes/comments added.
·
Jun 25, 2020
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pascal_spec7_v2
cfef5454
·
Merge branch 'pascal_spec7_v2' of
https://ohwr.org/project/wr-cores
into pascal_spec7_v2
·
May 19, 2020
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pascal_spec7_v1
0a312869
·
cleaned up code, removed deprecated stuff.
·
May 12, 2020
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tom-ertm14-apr27
c2bc0d5e
·
wrc_core: expose PHY LPC interface
·
Apr 27, 2020
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tom-afcz-mar20
2de3a3a1
·
wr_si57x_interface: made it working with SoftPLL on AFCZ.
·
Mar 20, 2020
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tom-ertm14-rebased
ee7a0f3d
·
platform: pre-validated version of kintex-7 lpdc phy
·
Mar 11, 2020
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pascal_spec7
2ce72bf5
·
Initial commit
·
Feb 21, 2020
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spec7_v1
67892968
·
Initial commit
·
Feb 07, 2020
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tom-jan30
4f8ec131
·
sim: fix whitespace error
·
Jan 31, 2020
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gsi_master_get_back_on_track_oct2020
74114272
·
xwr_softpll_ng: removed irq_o output
·
Jan 21, 2020
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tom-svec7-tests
26a3f9ea
·
svec7: bring back PLL aux clock, pll reference is 125 MHz
·
Dec 11, 2019
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tom-gthe4-zynqultrascale
fc94ea07
·
board: initial support for Xilinx ZCU106 devkit
·
Dec 06, 2019
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tom-dec03
e53a9335
·
xwrc_board: disable the blooody Etherbone core instantiation, adds a useless dependency!
·
Nov 25, 2019
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pascal_kc705
c2f6d4a4
·
fixed confilcts
·
Nov 19, 2019
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wrpc-v4.2_gsi_a10_cleanup
c1419c81
·
arria10: added html files to .gitignore
·
Nov 01, 2019
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hm-cute-dp
9f88f545
·
change ext_clk to clk_10m_ext_o.
·
Oct 21, 2019
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