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Wishbone slave generator
Commits
51d29598
Commit
51d29598
authored
Jul 17, 2012
by
Tomasz Wlostowski
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Plain Diff
wbgen_regbank.lua: avoid clock line assignments causing simulation errors
parent
c6850dc6
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1 changed file
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33 additions
and
29 deletions
+33
-29
wbgen_regbank.lua
wbgen_regbank.lua
+33
-29
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wbgen_regbank.lua
View file @
51d29598
...
@@ -48,7 +48,7 @@ function gen_hdl_code_monostable(field, reg)
...
@@ -48,7 +48,7 @@ function gen_hdl_code_monostable(field, reg)
field
.
ports
=
{
port
(
BIT
,
0
,
"out"
,
prefix
..
"_o"
,
"Port for MONOSTABLE field: '"
..
field
.
name
..
"' in reg: '"
..
reg
.
name
..
"'"
,
VPORT_REG
)
};
field
.
ports
=
{
port
(
BIT
,
0
,
"out"
,
prefix
..
"_o"
,
"Port for MONOSTABLE field: '"
..
field
.
name
..
"' in reg: '"
..
reg
.
name
..
"'"
,
VPORT_REG
)
};
field
.
acklen
=
3
;
field
.
acklen
=
3
;
field
.
extra_code
=
vsyncprocess
(
"
bus_clock_int
"
,
"rst_n_i"
,
{
field
.
extra_code
=
vsyncprocess
(
"
clk_sys_i
"
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_dly0"
,
0
);
va
(
prefix
..
"_dly0"
,
0
);
va
(
prefix
..
"_o"
,
0
);
va
(
prefix
..
"_o"
,
0
);
...
@@ -60,8 +60,8 @@ function gen_hdl_code_monostable(field, reg)
...
@@ -60,8 +60,8 @@ function gen_hdl_code_monostable(field, reg)
});
});
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
write_code
=
{
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
,
field
.
write_code
=
{
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
--
va(vi("rddata_reg", field.offset), vundefined()) };
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
field
.
ackgen_code
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
ackgen_code
=
{
va
(
prefix
..
"_int"
,
0
)
};
...
@@ -100,7 +100,7 @@ function gen_hdl_code_monostable(field, reg)
...
@@ -100,7 +100,7 @@ function gen_hdl_code_monostable(field, reg)
va
(
prefix
..
"_int_delay"
,
0
);
};
va
(
prefix
..
"_int_delay"
,
0
);
};
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
()),
field
.
write_code
=
{
--
va(vi("rddata_reg", field.offset), vundefined()),
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
va
(
prefix
..
"_int_delay"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
};
va
(
prefix
..
"_int_delay"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
};
...
@@ -126,7 +126,7 @@ function gen_hdl_code_bit(field, reg)
...
@@ -126,7 +126,7 @@ function gen_hdl_code_bit(field, reg)
field
.
signals
=
{
signal
(
BIT
,
0
,
prefix
..
"_int"
)
};
field
.
signals
=
{
signal
(
BIT
,
0
,
prefix
..
"_int"
)
};
field
.
acklen
=
1
;
field
.
acklen
=
1
;
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
()),
field
.
write_code
=
{
--
va(vi("rddata_reg", field.offset), vundefined()),
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_int"
)
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_int"
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
...
@@ -137,7 +137,7 @@ function gen_hdl_code_bit(field, reg)
...
@@ -137,7 +137,7 @@ function gen_hdl_code_bit(field, reg)
field
.
ports
=
{
port
(
BIT
,
0
,
"in"
,
prefix
..
"_i"
,
"Port for BIT field: '"
..
field
.
name
..
"' in reg: '"
..
reg
.
name
..
"'"
,
VPORT_REG
)
};
field
.
ports
=
{
port
(
BIT
,
0
,
"in"
,
prefix
..
"_i"
,
"Port for BIT field: '"
..
field
.
name
..
"' in reg: '"
..
reg
.
name
..
"'"
,
VPORT_REG
)
};
field
.
signals
=
{
};
field
.
signals
=
{
};
field
.
acklen
=
1
;
field
.
acklen
=
1
;
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
field
.
write_code
=
{
};
--
va(vi("rddata_reg", field.offset), vundefined()) };
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_i"
)
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_i"
)
};
field
.
reset_code_main
=
{
};
field
.
reset_code_main
=
{
};
field
.
extra_code
=
{
};
field
.
extra_code
=
{
};
...
@@ -158,7 +158,7 @@ function gen_hdl_code_bit(field, reg)
...
@@ -158,7 +158,7 @@ function gen_hdl_code_bit(field, reg)
field
.
acklen
=
1
;
field
.
acklen
=
1
;
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_i"
)
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_i"
)
};
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
()),
field
.
write_code
=
{
--
va(vi("rddata_reg", field.offset), vundefined()),
va
(
prefix
..
"_load_o"
,
1
)
};
va
(
prefix
..
"_load_o"
,
1
)
};
field
.
extra_code
=
{
va
(
prefix
..
"_o"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
field
.
extra_code
=
{
va
(
prefix
..
"_o"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
field
.
ackgen_code_pre
=
{
va
(
prefix
..
"_load_o"
,
0
)
};
field
.
ackgen_code_pre
=
{
va
(
prefix
..
"_load_o"
,
0
)
};
...
@@ -180,13 +180,13 @@ function gen_hdl_code_bit(field, reg)
...
@@ -180,13 +180,13 @@ function gen_hdl_code_bit(field, reg)
signal
(
BIT
,
0
,
prefix
..
"_sync1"
)
};
signal
(
BIT
,
0
,
prefix
..
"_sync1"
)
};
field
.
acklen
=
4
;
field
.
acklen
=
4
;
field
.
write_code
=
{
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
,
field
.
write_code
=
{
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
--
va(vi("rddata_reg", field.offset), vundefined()) };
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_int"
)
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_int"
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
field
.
extra_code
=
{
vcomment
(
"synchronizer chain for field : "
..
field
.
name
..
" (type RW/RO,
bus_clock_int
<-> "
..
field
.
clock
..
")"
);
field
.
extra_code
=
{
vcomment
(
"synchronizer chain for field : "
..
field
.
name
..
" (type RW/RO,
clk_sys_i
<-> "
..
field
.
clock
..
")"
);
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_o"
,
0
);
va
(
prefix
..
"_o"
,
0
);
...
@@ -209,12 +209,12 @@ function gen_hdl_code_bit(field, reg)
...
@@ -209,12 +209,12 @@ function gen_hdl_code_bit(field, reg)
signal
(
BIT
,
0
,
prefix
..
"_sync1"
)
};
signal
(
BIT
,
0
,
prefix
..
"_sync1"
)
};
field
.
acklen
=
1
;
field
.
acklen
=
1
;
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
())
};
field
.
write_code
=
{
};
--
va(vi("rddata_reg", field.offset), vundefined()) };
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_sync1"
)
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_sync1"
)
};
field
.
reset_code_main
=
{
};
field
.
reset_code_main
=
{
};
field
.
extra_code
=
{
vcomment
(
"synchronizer chain for field : "
..
field
.
name
..
" (type RO/WO, "
..
field
.
clock
..
" ->
bus_clock_int
)"
);
field
.
extra_code
=
{
vcomment
(
"synchronizer chain for field : "
..
field
.
name
..
" (type RO/WO, "
..
field
.
clock
..
" ->
clk_sys_i
)"
);
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_sync0"
,
0
);
va
(
prefix
..
"_sync0"
,
0
);
...
@@ -254,18 +254,19 @@ function gen_hdl_code_bit(field, reg)
...
@@ -254,18 +254,19 @@ function gen_hdl_code_bit(field, reg)
field
.
acklen
=
6
;
field
.
acklen
=
6
;
field
.
write_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
());
field
.
write_code
=
{
--
va(vi("rddata_reg", field.offset), vundefined());
va
(
prefix
..
"_int_write"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
va
(
prefix
..
"_int_write"
,
vi
(
"wrdata_reg"
,
field
.
offset
));
va
(
prefix
..
"_lw"
,
1
);
va
(
prefix
..
"_lw"
,
1
);
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_lw_read_in_progress"
,
0
);
va
(
prefix
..
"_lw_read_in_progress"
,
0
);
va
(
prefix
..
"_rwsel"
,
1
);
};
va
(
prefix
..
"_rwsel"
,
1
);
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
());
field
.
read_code
=
{
vif
(
vequal
(
"wb_we_i"
,
0
),
{
va
(
prefix
..
"_lw"
,
1
);
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
vundefined
());
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_lw"
,
1
);
va
(
prefix
..
"_lw_read_in_progress"
,
1
);
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_rwsel"
,
0
);
};
va
(
prefix
..
"_lw_read_in_progress"
,
1
);
va
(
prefix
..
"_rwsel"
,
0
);
}
);
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_lw"
,
0
);
field
.
reset_code_main
=
{
va
(
prefix
..
"_lw"
,
0
);
...
@@ -285,7 +286,7 @@ function gen_hdl_code_bit(field, reg)
...
@@ -285,7 +286,7 @@ function gen_hdl_code_bit(field, reg)
};
};
field
.
extra_code
=
{
vcomment
(
"asynchronous BIT register : "
..
field
.
name
..
" (type RW/WO, "
..
field
.
clock
..
" <->
bus_clock_int
)"
);
field
.
extra_code
=
{
vcomment
(
"asynchronous BIT register : "
..
field
.
name
..
" (type RW/WO, "
..
field
.
clock
..
" <->
clk_sys_i
)"
);
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_lw_s0"
,
0
);
va
(
prefix
..
"_lw_s0"
,
0
);
...
@@ -411,7 +412,7 @@ function gen_hdl_code_slv(field, reg)
...
@@ -411,7 +412,7 @@ function gen_hdl_code_slv(field, reg)
va
(
prefix
..
"_swb_delay"
,
0
);
};
va
(
prefix
..
"_swb_delay"
,
0
);
};
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RW/RO, "
..
field
.
clock
..
" <->
bus_clock_int
)"
);
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RW/RO, "
..
field
.
clock
..
" <->
clk_sys_i
)"
);
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_swb_s0"
,
0
);
va
(
prefix
..
"_swb_s0"
,
0
);
...
@@ -447,9 +448,10 @@ function gen_hdl_code_slv(field, reg)
...
@@ -447,9 +448,10 @@ function gen_hdl_code_slv(field, reg)
field
.
acklen
=
6
;
field
.
acklen
=
6
;
field
.
write_code
=
{
};
field
.
write_code
=
{
};
field
.
read_code
=
{
va
(
prefix
..
"_lwb"
,
1
);
field
.
read_code
=
{
vif
(
vequal
(
"wb_we_i"
,
0
),
{
va
(
prefix
..
"_lwb_delay"
,
1
);
va
(
prefix
..
"_lwb"
,
1
);
va
(
prefix
..
"_lwb_in_progress"
,
1
);
};
va
(
prefix
..
"_lwb_delay"
,
1
);
va
(
prefix
..
"_lwb_in_progress"
,
1
);
}
);
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_lwb"
,
0
);
field
.
reset_code_main
=
{
va
(
prefix
..
"_lwb"
,
0
);
va
(
prefix
..
"_lwb_delay"
,
0
);
va
(
prefix
..
"_lwb_delay"
,
0
);
...
@@ -464,7 +466,7 @@ function gen_hdl_code_slv(field, reg)
...
@@ -464,7 +466,7 @@ function gen_hdl_code_slv(field, reg)
});
});
};
};
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RO/WO, "
..
field
.
clock
..
" <->
bus_clock_int
)"
),
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RO/WO, "
..
field
.
clock
..
" <->
clk_sys_i
)"
),
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_lwb_s0"
,
0
);
va
(
prefix
..
"_lwb_s0"
,
0
);
...
@@ -516,10 +518,12 @@ function gen_hdl_code_slv(field, reg)
...
@@ -516,10 +518,12 @@ function gen_hdl_code_slv(field, reg)
va
(
prefix
..
"_lw_read_in_progress"
,
0
);
va
(
prefix
..
"_lw_read_in_progress"
,
0
);
va
(
prefix
..
"_rwsel"
,
1
);
};
va
(
prefix
..
"_rwsel"
,
1
);
};
field
.
read_code
=
{
va
(
prefix
..
"_lw"
,
1
);
field
.
read_code
=
{
vif
(
vequal
(
"wb_we_i"
,
0
),
{
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_lw"
,
1
);
va
(
prefix
..
"_lw_read_in_progress"
,
1
);
va
(
prefix
..
"_lw_delay"
,
1
);
va
(
prefix
..
"_rwsel"
,
0
);
};
va
(
prefix
..
"_lw_read_in_progress"
,
1
);
va
(
prefix
..
"_rwsel"
,
0
);
}
);
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_lw"
,
0
);
field
.
reset_code_main
=
{
va
(
prefix
..
"_lw"
,
0
);
...
@@ -538,7 +542,7 @@ function gen_hdl_code_slv(field, reg)
...
@@ -538,7 +542,7 @@ function gen_hdl_code_slv(field, reg)
});
});
};
};
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RW/WO, "
..
field
.
clock
..
" <->
bus_clock_int
)"
);
field
.
extra_code
=
{
vcomment
(
"asynchronous "
..
fieldtype_2_vhdl
[
field
.
type
]
..
" register : "
..
field
.
name
..
" (type RW/WO, "
..
field
.
clock
..
" <->
clk_sys_i
)"
);
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vsyncprocess
(
field
.
clock
,
"rst_n_i"
,
{
vreset
(
0
,
{
vreset
(
0
,
{
va
(
prefix
..
"_lw_s0"
,
0
);
va
(
prefix
..
"_lw_s0"
,
0
);
...
...
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