- 26 Sep, 2019 1 commit
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Dimitris Lampridis authored
partially re-apply 6ee9c2e0, some features (like wishbone records) got lost during the merge in 69883c7c
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- 04 May, 2018 1 commit
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Dimitris Lampridis authored
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- 20 Apr, 2018 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 18 Apr, 2018 4 commits
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Dimitris Lampridis authored
Some of the signals dropped in commit cc5a5c00 were actually being used when generating RAMs. They have been reintroduced, but this time only when generating RAMs.
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
- record_full interface option: use general cores's library WB interface types to simplify connection of the cores. Enabled by -H record_full option - use byte addressing for WB address (in record_full mode) - allow specifying package name with record/component definitions (hdl_package field in the peripheral record) - fixed indentation & formatting of produced VHDL package files - include VHDL component declaration in the package files
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- 24 Nov, 2017 1 commit
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Dimitris Lampridis authored
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- 03 Jul, 2017 1 commit
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Grzegorz Daniluk authored
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- 15 Jun, 2017 4 commits
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Dimitris Lampridis authored
vhdl: get rid of "internal signals for (foreseen) compatibility". They are not used and generate a ton of warnings
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Dimitris Lampridis authored
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Dimitris Lampridis authored
TODO: except texinfo doc output!
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Dimitris Lampridis authored
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- 14 Jun, 2017 1 commit
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Dimitris Lampridis authored
For now, the access from the bus is RW, we need to define a new RO/RO mode in wbgen.
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- 27 Apr, 2017 1 commit
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Dimitris Lampridis authored
target_pipelined_wb: in case of an if-generate, also add a second (complementary) if-generate to drive all outputs when the if-generate condition is false
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- 28 Aug, 2015 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@gmail.com> Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
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- 06 Aug, 2015 1 commit
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Grzegorz Daniluk authored
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- 07 Feb, 2014 1 commit
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Tomasz Wlostowski authored
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- 04 Dec, 2013 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 12 Nov, 2013 1 commit
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Tomasz Wlostowski authored
cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing synthesis error on Mentor Precision
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- 09 Sep, 2013 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 04 Jul, 2013 1 commit
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Tomasz Wlostowski authored
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- 25 Apr, 2013 1 commit
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Tomasz Wlostowski authored
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- 19 Apr, 2013 4 commits
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
initial support for 'optional' parameter (conditional instantiation of RAMs and FIFOs depending on a user-defined generic value)
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- 05 Apr, 2013 1 commit
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Tomasz Wlostowski authored
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- 12 Feb, 2013 1 commit
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Tomasz Wlostowski authored
fixed readback value of write-only (monostable) bits to 0. See Wesley's message on white-rabbit-dev, dated 12/02/2013 for explanation
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- 28 Jan, 2013 1 commit
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Tomasz Wlostowski authored
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- 05 Dec, 2012 1 commit
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Tomasz Wlostowski authored
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- 25 Oct, 2012 1 commit
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Tomasz Wlostowski authored
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- 17 Jul, 2012 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 26 Jun, 2012 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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