-
Tom Levens authored
Create a port (rst_n_o) on the top level component which is the combination of the HW resets (rst_n_i and VME_RST_n_i) and the SW reset bit coming from the CR/CSR. Signed-off-by: Tom Levens <tom.levens@cern.ch>
a293bef9
Create a port (rst_n_o) on the top level component which is the
combination of the HW resets (rst_n_i and VME_RST_n_i) and the SW reset
bit coming from the CR/CSR.
Signed-off-by: Tom Levens <tom.levens@cern.ch>
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Manifest.py | Loading commit data... | |
VME64xCore_Top.vhd | Loading commit data... | |
VME_Access_Decode.vhd | Loading commit data... | |
VME_Am_Match.vhd | Loading commit data... | |
VME_CRAM.vhd | Loading commit data... | |
VME_CR_CSR_Space.vhd | Loading commit data... | |
VME_Funct_Match.vhd | Loading commit data... | |
VME_IRQ_Controller.vhd | Loading commit data... | |
VME_User_CSR.vhd | Loading commit data... | |
VME_Wb_master.vhd | Loading commit data... | |
VME_bus.vhd | Loading commit data... | |
VME_swapper.vhd | Loading commit data... | |
vme64x_pack.vhd | Loading commit data... | |
xvme64x_core.vhd | Loading commit data... | |
xvme64x_core_pkg.vhd | Loading commit data... |