Commits · ffb421dd77d5c268c664d993452c38f0a0f299d4 · Projects / VME64x core · GitLab

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Apr 24, 2020
- top_tb: remap ram. · ffb421dd
  Tristan Gingold authored 5 years ago
  
  ffb421dd
- vme_bus: improve timing. · 9d43711f
  Tristan Gingold authored 5 years ago
  
  9d43711f
- top_tb: add a test for 2eSST. · 0b0209c1
  Tristan Gingold authored 5 years ago
  
  0b0209c1
- vme: preliminary support of 2eSST. · 9388296e
  Tristan Gingold authored 5 years ago
  
  9388296e
- vme_bus: add setup time. · e02c9e0f
  Tristan Gingold authored 5 years ago
  
  e02c9e0f
- vme_bus: add asynchronous control of dtack. · ef710744
  Tristan Gingold authored 5 years ago
  
  ef710744
- vme_bus: add raw ds input. · a9f18940
  Tristan Gingold authored 5 years ago
  
  a9f18940
- vme_bus: make dtack output explicitely latched. · 8a4cc17f
  Tristan Gingold authored 5 years ago
  
  8a4cc17f
- simple_tb: add one transaction. · 65121f5a
  Tristan Gingold authored 5 years ago
  
  65121f5a
- vme_bus: precharge data. · d7c03c1b
  Tristan Gingold authored 5 years ago
  
  d7c03c1b
- vme_bus: improve direction driving. · c4e8308e
  Tristan Gingold authored 5 years ago
  
  c4e8308e
- vme_bus: cleanup · 73230942
  Tristan Gingold authored 5 years ago
  
  73230942
- vme_bus: cleanup · 29b8b02b
  Tristan Gingold authored 5 years ago
  
  29b8b02b
- vme_bus: simulation is OK. · 60f29f5d
  Tristan Gingold authored 5 years ago
  
  60f29f5d
- top_tb: add debug code. · a006c850
  Tristan Gingold authored 5 years ago
  
  a006c850
- vme_bus: new prefetch. · c8c501f5
  Tristan Gingold authored 5 years ago
  
  c8c501f5
- simple_tb: simulate propagation for dtack. · e9ae25eb
  Tristan Gingold authored 5 years ago
  
  e9ae25eb
- vme_bus: renaming. · 2cdedc10
  Tristan Gingold authored 5 years ago
  
  2cdedc10
- vme_bus: reformatting. · b5476928
  Tristan Gingold authored 5 years ago
  
  b5476928
- Add vme_bus.vhd original modifications from Milos Vojinovic. · a5b91e65
  Tristan Gingold authored 5 years ago
  
  a5b91e65
- Reference general-cores with a git module. · 350d15cc
  Tristan Gingold authored 5 years ago
  
  350d15cc
Apr 14, 2020
- simple_tb: improve run_all.sh · 9a4a5b11
  Tristan Gingold authored 4 years ago
  
  9a4a5b11
- simple_tb/Manifest.py: use git module for general-cores · d9342f87
  Tristan Gingold authored 4 years ago
  
  d9342f87
Nov 14, 2019
- Add a comment. · 6abee52c
  Tristan Gingold authored 5 years ago
  
  6abee52c
Nov 11, 2019
- Add vme16_tb testbench · 7b94b276
  Tristan Gingold authored 5 years ago
  
  7b94b276
- Add ghdl support for simple_tb. · 2736fdff
  Tristan Gingold authored 5 years ago
  
  2736fdff
- vme64x_pkg: rename c_AM_A24_S to c_AM_A24 · a994813b
  Tristan Gingold authored 5 years ago
  
  a994813b
- vme64x_core: add g_VME32 generic (true by default). · b9f87fb9
  Tristan Gingold authored 5 years ago
```
Add support for a D16 only (still with D8) core.
```
  b9f87fb9
- top_tb: add entity name after 'end' for the sake of hdlmake. · 84da9bdd
  Tristan Gingold authored 5 years ago
  
  84da9bdd
Jul 24, 2019
- simple_tb: adjust scenario 9. · 366ca4db
  Tristan Gingold authored 5 years ago
  
  366ca4db
- sim: cleanup in vme bfm. · 3dd0b23a
  Tristan Gingold authored 5 years ago
  
  3dd0b23a
- xvme64x_core: add g_WB_MODE generic to select between classic/pipelined. · 4d39f9df
  Tristan Gingold authored 5 years ago
  
  4d39f9df
Apr 02, 2019
- Update general-cores submodule URL for new OHWR · 1204aeca
  Tom Levens authored 5 years ago
  
  1204aeca
Nov 29, 2018
- Invert RTY assertion logic to make simulators happier · 78cac871
  Dimitris Lampridis authored 6 years ago
  
  78cac871
Oct 26, 2018
- Implement amnesia address if parity is wrong · e0f5eaad
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  e0f5eaad
- Add new generic to component declaration · ae052e76
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  ae052e76
- Cleanup alignment of code · c3d44ce4
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  c3d44ce4
- Fix references to ANSI/VITA standards · 45cb91f4
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  45cb91f4
Oct 25, 2018
- Add generic to disable CR/CSR · 44f9345f
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  44f9345f
- Normalise case of generics and ports · a2ee4ac4
  Tom Levens authored 6 years ago
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  a2ee4ac4