vme_bus.vhd: add an intermediate signal to ease probing (ILA)

Fix a typo in a comment

hdl/rtl/vme_bus.vhd

@@ -140,6 +140,7 @@ architecture rtl of vme_bus is
 
   signal vme_odff_dtack_n          : std_logic;
   signal vme_odff_dtack_oe         : std_logic;
+  signal vme_dtack_n_out           : std_logic;
 
   signal vme_odff_retry_n          : std_logic;
   signal vme_odff_retry_oe         : std_logic;
@@ -274,6 +275,8 @@ architecture rtl of vme_bus is
   signal s_wb_done              : std_logic;
   signal s_wb_start             : std_logic;
 
+  signal wb_stb_out             : std_logic;
+  
   --  Set if the next WB access will cross boundary for BLT/MBLT
   --  transfer.  It will prevent from doing the next transfer.
   signal s_cross_boundary : std_logic;
@@ -919,7 +922,7 @@ begin
         s_WBFSMstate  <= IDLE;
         -- WB
         wb_cyc_o         <= '0';
-        wb_stb_o         <= '0';
+        wb_stb_out       <= '0';
         wb_sel_o         <= "0000";
         wb_we_o          <= '0';
         addr_reg         <= (others => '0');
@@ -933,7 +936,7 @@ begin
           when IDLE =>
 
             wb_cyc_o <= '0';
-            wb_stb_o <= '0';
+            wb_stb_out <= '0';
 
             if load_addr_reg_phase1 = '1' then
               --  VME address phase 1.
@@ -982,7 +985,7 @@ begin
             if s_wb_start = '1' and s_cross_boundary = '0' then
               -- Start WB cycle.
               wb_cyc_o <= s_card_sel;
-              wb_stb_o <= s_card_sel;
+              wb_stb_out <= s_card_sel;
               wb_we_o <= not vme_idff_write_n;
 
               if vme_idff_write_n = '0' then
@@ -1072,10 +1075,10 @@ begin
             case g_WB_MODE is
               when CLASSIC =>
                 -- Maintain STB.
-                wb_stb_o <= '1';
+                wb_stb_out <= '1';
               when PIPELINED =>
                 -- Maintain STB if stall was set in the previous cycle.
-                wb_stb_o <= s_stall and wb_stall_i;
+                wb_stb_out <= s_stall and wb_stall_i;
             end case;
 
             s_stall  <= s_stall and wb_stall_i;
@@ -1083,7 +1086,7 @@ begin
             if wb_ack_i = '1' or wb_err_i = '1' then
               -- WB ack
               -- For classic mode, be sure strobe is negated.
-              wb_stb_o <= '0';
+              wb_stb_out <= '0';
 
               if s_transferType /= SINGLE then
                 --  Next word for any block transfer.
@@ -1146,7 +1149,7 @@ begin
                       s_WBFSMstate <= MEMORY_PAUSE;
                     when PIPELINED =>
                       -- No need to pause, can directly start a new xfer.
-                      wb_stb_o <= '1';
+                      wb_stb_out <= '1';
                       s_stall  <= '1';
                       s_WBFSMstate <= MEMORY_REQ;
                   end case;
@@ -1163,10 +1166,10 @@ begin
           when MEMORY_PAUSE =>
             -- Wait until ACK is 0. Strictly speaking, this is not needed
             -- according to WB specs.
-            wb_stb_o <= '0';
+            wb_stb_out <= '0';
 
             if wb_ack_i = '0' then
-              wb_stb_o <= '1';
+              wb_stb_out <= '1';
               s_stall  <= '1';
               s_WBFSMstate <= MEMORY_REQ;
             else
@@ -1218,11 +1221,14 @@ begin
   process (vme_odff_dtack_n, vme_nsync_ds_n_i, vme_dtack_async_ctrl)
   begin
     if vme_dtack_async_ctrl = '0' or not g_ASYNC_DTACK then
-      vme_dtack_n_o <= vme_odff_dtack_n;
+      vme_dtack_n_out <= vme_odff_dtack_n;
     else
       --  Asserted (to 0) as soon as one ds signal is asserted (to 0).
       --  Negated (to 1) as soon as both ds signal is negated (to 1).
-      vme_dtack_n_o <= vme_nsync_ds_n_i(0) and vme_nsync_ds_n_i(1);
+      vme_dtack_n_out <= vme_nsync_ds_n_i(0) and vme_nsync_ds_n_i(1);
     end if;
   end process;
+
+  vme_dtack_n_o <= vme_dtack_n_out;
+  wb_stb_o <= wb_stb_out;
 end rtl;

hdl/rtl/xvme64x_core.vhd

@@ -72,7 +72,7 @@ entity xvme64x_core is
     --  But it then requires a minimal frequency, otherwise the master may
     --  change the bus before the slave latched the data.
     --  No problems have been reported when the clock is faster than 62.5Mhz.
-    --  Problems have been repored for clock slower than 40Mhz.
+    --  Problems have been reported for clock slower than 40Mhz.
     g_ASYNC_DTACK     : boolean := False;
 
     -- Address granularity on the WB bus. Value can be: