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urv-core
Commit c776e4c1 authored by Tristan Gingold's avatar Tristan Gingold
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urv: add mpie, restore on mret.

parent 9e186e33
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Showing with 31 additions and 19 deletions
rtl/urv_exceptions.v
View file @ c776e4c1
...@@ -66,15 +66,19 @@ module urv_exceptions ...@@ -66,15 +66,19 @@ module urv_exceptions
reg [31:0] csr_mepc; reg [31:0] csr_mepc;
reg [31:0] csr_mie; reg [31:0] csr_mie;
reg csr_status_mie; reg csr_status_mie;
reg csr_status_mpie;
reg [3:0] csr_mcause_code; reg [3:0] csr_mcause_code;
reg csr_mcause_interrupt; reg csr_mcause_interrupt;
assign csr_mcause_o = {csr_mcause_interrupt, 27'h0, csr_mcause_code}; assign csr_mcause_o = {csr_mcause_interrupt, 27'h0, csr_mcause_code};
assign csr_mepc_o = csr_mepc; assign csr_mepc_o = csr_mepc;
assign csr_mie_o = csr_mie; assign csr_mie_o = csr_mie;
assign csr_mstatus_o[3] = csr_status_mie;
assign csr_mstatus_o[31:4] = 0;
assign csr_mstatus_o[2:0] = 0; assign csr_mstatus_o[2:0] = 0;
assign csr_mstatus_o[3] = csr_status_mie;
assign csr_mstatus_o[6:4] = 0;
assign csr_mstatus_o[7] = csr_status_mpie;
assign csr_mstatus_o[31:8] = 0;
assign csr_mip_o = 0; assign csr_mip_o = 0;
...@@ -89,6 +93,7 @@ module urv_exceptions ...@@ -89,6 +93,7 @@ module urv_exceptions
csr_mepc <= 0; csr_mepc <= 0;
csr_mie <= 0; csr_mie <= 0;
csr_status_mie <= 0; csr_status_mie <= 0;
csr_status_mpie <= 0;
end end
else else
begin begin
...@@ -98,25 +103,32 @@ module urv_exceptions ...@@ -98,25 +103,32 @@ module urv_exceptions
csr_mcause_code <= x_exception_cause_i; csr_mcause_code <= x_exception_cause_i;
csr_mcause_interrupt <= x_interrupt_i; csr_mcause_interrupt <= x_interrupt_i;
// Mask interrupts when taken. // Mask interrupts during exceptions
if (x_interrupt_i) csr_status_mpie <= csr_status_mie;
csr_status_mie <= 0; csr_status_mie <= 0;
end end
if (!x_stall_i && !x_kill_i && d_is_csr_i) if (!x_stall_i && !x_kill_i)
case (d_csr_sel_i) begin
`CSR_ID_MSTATUS: if (d_is_csr_i)
csr_status_mie <= x_csr_write_value_i[3]; case (d_csr_sel_i)
`CSR_ID_MEPC: `CSR_ID_MSTATUS:
csr_mepc <= x_csr_write_value_i; csr_status_mie <= x_csr_write_value_i[3];
`CSR_ID_MIE: `CSR_ID_MEPC:
begin csr_mepc <= x_csr_write_value_i;
csr_mie[`EXCEPT_TIMER] <= x_csr_write_value_i[`EXCEPT_TIMER]; `CSR_ID_MIE:
csr_mie[`EXCEPT_IRQ] <= x_csr_write_value_i[`EXCEPT_IRQ]; begin
end csr_mie[`EXCEPT_TIMER] <=
endcase // case (d_csr_sel_i) x_csr_write_value_i[`EXCEPT_TIMER];
end // if (d_is_csr_i) csr_mie[`EXCEPT_IRQ] <=
x_csr_write_value_i[`EXCEPT_IRQ];
end
endcase
if (d_is_mret_i)
csr_status_mie <= csr_status_mpie;
end
end
assign x_exception_pc_o = csr_mepc; assign x_exception_pc_o = csr_mepc;
......
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