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Commit 706d34d2 authored by Tristan Gingold's avatar Tristan Gingold
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sw: add a write_ecc test

parent c824038b
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Showing with 104 additions and 9 deletions
sw/common/irq.S
View file @ 706d34d2
.section .text
.global trap_entry
.global trap_entry
.weak trap_entry
trap_entry:
csrrw sp,mscratch,sp
addi sp,sp,-320
......
sw/testsuite/isa/Makefile
View file @ 706d34d2
......@@ -13,6 +13,7 @@ isa_src_dir := .
include $(isa_src_dir)/rv32ui/Makefrag
#include $(isa_src_dir)/rv32si/Makefrag
include $(isa_src_dir)/rv32mi/Makefrag
include $(isa_src_dir)/urv/Makefrag
default: all
......@@ -68,6 +69,7 @@ tests += $$($(1)_tests)
endef
$(eval $(call compile_template,rv32ui,))
$(eval $(call compile_template,urv,))
tests_dump = $(addsuffix .dump, $(tests))
tests_ram = $(addsuffix .ram, $(tests))
......
sw/testsuite/isa/urv/Makefrag 0 → 100644
View file @ 706d34d2
#=======================================================================
# Makefrag for rv32ui tests
#-----------------------------------------------------------------------
urv_ecc_tests = \
write_ecc
urv_p_tests = $(addprefix urv-p-, $(urv_ecc_tests))
spike_tests += $(urv_p_tests)
sw/testsuite/isa/urv/write_ecc.S 0 → 100644
View file @ 706d34d2
# See LICENSE for license details.
#*****************************************************************************
# write_ecc.S
#-----------------------------------------------------------------------------
#
# Test write_ecc trap.
#
#include "riscv_test.h"
#include "test_macros.h"
#define write_ecc(rd,rs1,rs2) \
.long 0x5b | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (1 << 12)
RVTEST_RV32S
RVTEST_CODE_BEGIN
li TESTNUM, 2
li t2, 0 #t2 is reg 7
# No bad ECC
write_ecc(7,7,7)
nop # avoid bypass
nop
nop
# Use reg 7
addi t2,t2,1
j 1f # Not skipped
j fail
1: li t2, 2
li t1, 1 #t1 is reg 6
# Write bad ECC for reg 7
write_ecc(7,7,6)
nop # avoid bypass
nop
nop
# Use reg 7
addi t2,t2,1
j fail # Skipped by handler
li t1, 2
li t2, 3
# Write bad ECC for reg 7
write_ecc(7,7,6)
nop # avoid bypass
nop
nop
# Use reg 7
add t3,t2,t2
j fail # Skipped by handler
j pass
TEST_PASSFAIL
.globl trap_entry
trap_entry:
# Destroy t1, t0
li t1, CAUSE_ECC_ERROR
csrr t0, mcause
bne t0, t1, fail
# Inc address by 8
csrr t0, mepc
addi t0, t0, 8
csrw mepc, t0
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
tb/isa-testsuite/main.sv
View file @ 706d34d2
......@@ -24,11 +24,11 @@
`timescale 1ns/1ps
localparam struct {
bit mul;
bit div;
bit dbg;
bit ws;
bit ecc;
bit mul;
bit div;
bit dbg;
bit ws;
bit ecc;
} configs[6] = '{ '{ mul: 0, div: 0, dbg: 0, ws: 0, ecc: 0 },
'{ mul: 0, div: 0, dbg: 0, ws: 1, ecc: 1 },
'{ mul: 1, div: 0, dbg: 0, ws: 0, ecc: 1 },
......@@ -97,13 +97,15 @@ module ICpuTestWrapper
automatic string rv;
if(configs[r_active_cpu].mul)
rv = {rv, "hw_mulh"};
rv = {rv, " hw_mulh"};
if(configs[r_active_cpu].div)
rv = {rv, " hw_div"};
if(configs[r_active_cpu].dbg)
rv = {rv, " hw_debug"};
if(configs[r_active_cpu].ws)
rv = {rv, " wait_state"};
if(configs[r_active_cpu].ecc)
rv = {rv, " ecc"};
return rv;
......@@ -204,7 +206,8 @@ module ICpuTestWrapper
#(
.g_with_hw_mulh(configs[i].mul),
.g_with_hw_div(configs[i].div),
.g_with_hw_debug(configs[i].dbg)
.g_with_hw_debug(configs[i].dbg),
.g_with_ecc(configs[i].ecc)
)
DUTx
(
......@@ -375,9 +378,11 @@ endclass // ISATestRunner
begin
DUT.selectConfiguration(i);
l.startTest($sformatf( "Full ISA Test for feature set [%s]", DUT.getConfigurationString() ) );
l.startTest($sformatf( "Full ISA Test for feature set:%s", DUT.getConfigurationString() ) );
testRunner.runAllTests("../../sw/testsuite/isa", "tests.lst" );
if (configs[i].ecc)
testRunner.runAllTests("../../sw/testsuite/isa", "tests-urv.lst" );
end
l.writeTestReport("report.txt");
......
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