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urv-core
Commit 4a459e87 authored by Tristan Gingold's avatar Tristan Gingold
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rtl: simplify urv_decode and urv_exec

parent 98e08ba0
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Showing with 11 additions and 17 deletions
rtl/urv_decode.v
View file @ 4a459e87
...@@ -314,9 +314,9 @@ module urv_decode ...@@ -314,9 +314,9 @@ module urv_decode
case (d_opcode) case (d_opcode)
`OPC_OP: `OPC_OP:
x_is_add_o <= ~f_ir_i[30] && !(d_fun == `FUNC_SLT || d_fun == `FUNC_SLTU); x_is_add_o <= ~f_ir_i[30];
`OPC_OP_IMM: `OPC_OP_IMM:
x_is_add_o <= !(d_fun == `FUNC_SLT || d_fun == `FUNC_SLTU); x_is_add_o <= 1;
`OPC_BRANCH: `OPC_BRANCH:
x_is_add_o <= 0; x_is_add_o <= 0;
default: default:
......
rtl/urv_exec.v
View file @ 4a459e87
...@@ -263,26 +263,20 @@ module urv_exec ...@@ -263,26 +263,20 @@ module urv_exec
wire [32:0] alu_addsub_op1 = {d_is_signed_alu_op_i ? alu_op1[31] : 1'b0, alu_op1 }; wire [32:0] alu_addsub_op1 = {d_is_signed_alu_op_i ? alu_op1[31] : 1'b0, alu_op1 };
wire [32:0] alu_addsub_op2 = {d_is_signed_alu_op_i ? alu_op2[31] : 1'b0, alu_op2 }; wire [32:0] alu_addsub_op2 = {d_is_signed_alu_op_i ? alu_op2[31] : 1'b0, alu_op2 };
reg [32:0] alu_addsub_result;
// ALU adder/subtractor // ALU adder/subtractor
always@* wire [32:0] alu_add = alu_addsub_op1 + alu_addsub_op2;
if(d_is_add_i) wire [32:0] alu_sub = alu_addsub_op1 - alu_addsub_op2;
alu_addsub_result <= alu_addsub_op1 + alu_addsub_op2;
else
alu_addsub_result <= alu_addsub_op1 - alu_addsub_op2;
// the rest of the ALU // the rest of the ALU
always@* always@*
case (d_fun_i) case (d_fun_i)
`FUNC_ADD: alu_result <= alu_addsub_result[31:0]; `FUNC_ADD: alu_result <= d_is_add_i ? alu_add[31:0] : alu_sub[31:0];
`FUNC_XOR: alu_result <= alu_op1 ^ alu_op2; `FUNC_XOR: alu_result <= alu_op1 ^ alu_op2;
`FUNC_OR: alu_result <= alu_op1 | alu_op2; `FUNC_OR: alu_result <= alu_op1 | alu_op2;
`FUNC_AND: alu_result <= alu_op1 & alu_op2; `FUNC_AND: alu_result <= alu_op1 & alu_op2;
`FUNC_SLT: alu_result <= alu_addsub_result[32]?1:0; `FUNC_SLT,
`FUNC_SLTU: alu_result <= alu_addsub_result[32]?1:0; `FUNC_SLTU: alu_result <= {31'b0, alu_sub[32]};
default: alu_result <= 32'hx; default: alu_result <= 32'hx;
endcase // case (d_fun_i) endcase // case (d_fun_i)
// barel shifter // barel shifter
......
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