feat[fusesoc]: adding FuseSoC support

This branch will add FuseSoC support to urv. The submodule path to general-cores has also been updated to point at the NQ branch.

feat[fusesoc]: adding FuseSoC support
This branch will add FuseSoC support to urv. The submodule path to general-cores has also been updated to point at the NQ branch.
44511c82 · Shareef Jalloq · 65e80de2 · 44511c82 · 44511c82 · 44511c82
Commit 44511c82 authored Feb 03, 2024 by Shareef Jalloq
12 changed files
--- a/.gitignore
+++ b/.gitignore
+/build/
+.vscode
+.venv
+docs/build
\ No newline at end of file
--- a/.gitmodules
+++ b/.gitmodules
 [submodule "ip_cores/general-cores"]
 	path = ip_cores/general-cores
-	url = git://ohwr.org/hdl-core-lib/general-cores.git
+	url = https://ohwr.org/project/general-cores.git
--- a/docs/Makefile
+++ b/docs/Makefile
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS    ?=
+SPHINXBUILD   ?= sphinx-build
+SOURCEDIR     = source
+BUILDDIR      = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
+# Configuration file for the Sphinx documentation builder.
+#
+# For the full list of built-in configuration values, see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Project information -----------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
+
+project = 'uRV'
+copyright = '2024, ohwr.org'
+author = 'ohwr.org'
+
+# -- General configuration ---------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
+
+extensions = []
+
+templates_path = ['_templates']
+exclude_patterns = []
+
+
+
+# -- Options for HTML output -------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
+
+html_theme = 'alabaster'
+html_static_path = ['_static']
--- a/docs/source/getting_started.rst
+++ b/docs/source/getting_started.rst
+..  Headings guide:
+    # with overline, for parts
+    * with overline, for chapters
+    = for sections
+    - for subsections
+    ^ for subsubsections
+    " for paragraphs
+
+###############
+Getting Started
+###############
+
+Not much here for now.
+
+.. code-block:: 
+
+    git clone https://ohwr.org/project/urv-core.git
+    cd urv-code
+    . sourceme
+    fusesoc list-cores
+
+**********************
+Running Verilator Lint
+**********************
+
+.. code-block::
+
+    fusesoc run --target lint ohwr:urv:urv_cpu
+
+    
\ No newline at end of file
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
+.. uRV documentation master file, created by
+   sphinx-quickstart on Mon Feb  5 01:42:25 2024.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+Welcome to uRV's documentation!
+===============================
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   getting_started.rst
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`modindex`
+* :ref:`search`
--- a/lint/urv_cpu.vlt
+++ b/lint/urv_cpu.vlt
+`verilator_config
+
+// REVISIT: these all need fixing but just waived for now.
+lint_off --rule DECLFILENAME --file "*/urv_*.v"
+lint_off --rule COMBDLY --file "*/urv_*.v"
+lint_off --rule CASEINCOMPLETE --file "*/urv_csr.v"
+lint_off --rule CASEINCOMPLETE --file "*/urv_exceptions.v"
+lint_off --rule UNUSED --file "*/urv_*.v"
+lint_off --rule WIDTH --file "*/urv_multiply.v"
+lint_off --rule GENUNNAMED --file "*/urv_*.v"
+
+// Use of integer parameter causes width mismatch; ignore.
+lint_off --rule WIDTH --file "*/urv_decode.v" --match "*g_with_hw_mul*"
+lint_off --rule WIDTH --file "*/urv_timer.v" --match "*'presc' generates 24 bits."
+lint_off --rule WIDTH --file "*/urv_exec.v" --match "*g_with_hw_mul*"
--- a/requirements.txt
+++ b/requirements.txt
+# Fusesoc and Edalize for tool flows
+fusesoc
+edalize
+
+# Git hooks
+pre-commit
+
+# Documentation
+sphinx
\ No newline at end of file
--- a/sourceme
+++ b/sourceme
+CWD="$(cd -- "$(dirname "${BASH_SOURCE[0]}")" >/dev/null && pwd -P )"
+VENV=.venv
+
+if [[ ! -e $VENV ]]; then
+    python3 -m venv $VENV
+    source $VENV/bin/activate
+    pip install -U pip wheel
+    pip install -r requirements.txt
+else
+    source $VENV/bin/activate
+fi
+
+# pre-commit install
+
+export FUSESOC_CORES=$CWD
\ No newline at end of file
--- a/urv_core.core
+++ b/urv_core.core
+CAPI=2:
+name: ohwr:urv:xurv_core
+description: Top level VHDL integration module
+
+filesets:
+  rtl:
+    depend:
+      - ohwr:general-cores:gencores_pkg
+      - ohwr:general-cores:genram_pkg
+      - ohwr:general-cores:wishbone_pkg
+      - ohwr:urv:urv_pkg
+      - ohwr:urv:urv_cpu
+    files:
+      - rtl/urv_iram.v: { file_type: verilogSource }
+      - rtl/xurv_core.vhd: { file_type: vhdlSource }
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel: xurv_core
+
+  synth:
+    <<: *default
+    default_tool: vivado
+    tools:
+      vivado:
+        part: xc7z030ffg676-3
\ No newline at end of file
--- a/urv_cpu.core
+++ b/urv_cpu.core
+CAPI=2:
+name: ohwr:urv:urv_cpu
+description: CPU Core level of uRV 
+
+filesets:
+  rtl:
+    files:
+      - rtl/urv_defs.v: { is_include_file: true }
+      - rtl/urv_config.v: { is_include_file: true }
+      - rtl/urv_exec.v
+      - rtl/urv_fetch.v
+      - rtl/urv_decode.v
+      - rtl/urv_regfile.v
+      - rtl/urv_writeback.v
+      - rtl/urv_shifter.v
+      - rtl/urv_multiply.v
+      - rtl/urv_divide.v
+      - rtl/urv_csr.v
+      - rtl/urv_timer.v
+      - rtl/urv_exceptions.v
+      - rtl/urv_ecc.v
+      - rtl/urv_cpu.v
+    file_type: verilogSource
+
+  verilator_waivers:
+    files:
+      - lint/urv_cpu.vlt
+    file_type: vlt
+
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+      - tool_verilator? (verilator_waivers)
+    toplevel: urv_cpu
+
+  lint:
+    <<: *default
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - -Wall
\ No newline at end of file
--- a/urv_pkg.core
+++ b/urv_pkg.core
+CAPI=2:
+name: ohwr:urv:urv_pkg
+description: uRV VHDL Package
+
+filesets:
+  rtl:
+    files:
+      - rtl/urv_pkg.vhd
+    file_type: vhdlSource
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+