Skip to content

U
urv-core
Commit 134759b2 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

Simplify debug interface.

parent c701e7ca
Hide whitespace changes
Inline Side-by-side
Showing with 39 additions and 79 deletions
rtl/urv_cpu.v
View file @ 134759b2
......@@ -66,22 +66,19 @@ module urv_cpu
input dbg_force_i,
output dbg_enabled_o,
input [31:0] dbg_insn_i,
input dbg_insn_set_i,
output dbg_insn_ready_o,
input [31:0] dbg_mbxi_data_i,
input dbg_mbxi_write_i,
output dbg_mbxi_full_o,
output [31:0] dbg_mbxo_data_o,
input dbg_mbxo_read_i,
output dbg_mbxo_full_o
input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o
);
// pipeline control
wire f_stall;
wire w_stall;
wire x_stall;
wire x_kill;
wire f_kill;
wire d_stall;
wire d_kill;
wire d_stall_req;
......@@ -175,6 +172,8 @@ module urv_cpu
.dbg_force_i(dbg_force_i),
.dbg_enabled_o(dbg_enabled_o),
.dbg_insn_i(dbg_insn_i),
.dbg_insn_set_i(dbg_insn_set_i),
.dbg_insn_ready_o(dbg_insn_ready_o),
.x_dbg_toggle(x2f_dbg_toggle)
);
......@@ -332,12 +331,9 @@ module urv_cpu
.timer_tick_i (sys_tick),
// Debug mailboxes
.dbg_mbxi_data_i(dbg_mbxi_data_i),
.dbg_mbxi_write_i(dbg_mbxi_write_i),
.dbg_mbxi_full_o(dbg_mbxi_full_o),
.dbg_mbxo_data_o(dbg_mbxo_data_o),
.dbg_mbxo_read_i(dbg_mbxo_read_i),
.dbg_mbxo_full_o(dbg_mbxo_full_o)
.dbg_mbx_data_i(dbg_mbx_data_i),
.dbg_mbx_write_i(dbg_mbx_write_i),
.dbg_mbx_data_o(dbg_mbx_data_o)
);
// Execute 2/Writeback stage
......@@ -347,7 +343,6 @@ module urv_cpu
.rst_i(rst_i),
// pipe control
.w_stall_i(w_stall),
.w_stall_req_o(w_stall_req),
// from X1 stage
......@@ -405,9 +400,8 @@ module urv_cpu
// pipeline control
assign f_stall = x_stall_req || w_stall_req || d_stall_req;
assign x_stall = x_stall_req || w_stall_req;
assign d_stall = x_stall_req || w_stall_req;
assign w_stall = 0;
assign x_stall = x_stall_req || w_stall_req;
assign x_kill = x2f_bra || x2f_bra_d0 || x2f_bra_d1;
assign d_kill = x2f_bra || x2f_bra_d0;
......
rtl/urv_csr.v
View file @ 134759b2
......@@ -55,20 +55,13 @@ module urv_csr
input [31:0] csr_mcause_i,
// Debug mailboxes
input [31:0] dbg_mbxi_data_i,
input dbg_mbxi_write_i,
output dbg_mbxi_full_o,
output [31:0] dbg_mbxo_data_o,
input dbg_mbxo_read_i,
output dbg_mbxo_full_o
input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o
);
reg [31:0] csr_mscratch;
reg [31:0] csr_dbg_scratch;
reg [31:0] mbxo_data;
reg [31:0] mbxi_data;
reg mbxo_valid;
reg mbxi_valid;
reg [31:0] mbx_data;
reg [31:0] csr_in1;
reg [31:0] csr_in2;
......@@ -87,10 +80,7 @@ module urv_csr
`CSR_ID_MCAUSE: csr_in1 <= csr_mcause_i;
`CSR_ID_MIP: csr_in1 <= csr_mip_i;
`CSR_ID_MIE: csr_in1 <= csr_mie_i;
`CSR_ID_DBGSTATUS: csr_in1 <= {30'b0, mbxo_valid, mbxi_valid};
`CSR_ID_DBGSCRATCH: csr_in1 <= csr_dbg_scratch;
`CSR_ID_DBGMBXI: csr_in1 <= mbxi_data;
`CSR_ID_DBGMBXO: csr_in1 <= mbxo_data;
`CSR_ID_DBGMBX: csr_in1 <= mbx_data;
default: csr_in1 <= 32'hx;
endcase // case (d_csr_sel_i)
......@@ -128,41 +118,23 @@ module urv_csr
if(rst_i)
begin
csr_mscratch <= 0;
csr_dbg_scratch <= 0;
mbxo_data <= 0;
mbxi_data <= 0;
mbxo_valid <= 0;
mbxi_valid <= 0;
mbx_data <= 0;
end
else
begin
if (dbg_mbxo_read_i)
mbxo_valid <= 0;
if (dbg_mbxi_write_i)
begin
mbxi_data <= dbg_mbxi_data_i;
mbxi_valid <= 1;
end
if (dbg_mbx_write_i)
mbx_data <= dbg_mbx_data_i;
if(!x_stall_i && !x_kill_i && d_is_csr_i)
case (d_csr_sel_i)
`CSR_ID_MSCRATCH:
csr_mscratch <= csr_out;
`CSR_ID_DBGSCRATCH:
csr_dbg_scratch <= csr_out;
`CSR_ID_DBGMBXO:
begin
mbxo_data <= csr_out;
mbxo_valid <= 1;
end
`CSR_ID_DBGMBXI:
mbxi_valid <= 0;
`CSR_ID_DBGMBX:
mbx_data <= csr_out;
endcase // case (d_csr_sel_i)
end // else: !if(rst_i)
assign dbg_mbxo_data_o = mbxo_data;
assign dbg_mbxo_full_o = mbxo_valid;
assign dbg_mbxi_full_o = mbxi_valid;
assign dbg_mbx_data_o = mbx_data;
assign x_csr_write_value_o = csr_out;
endmodule
rtl/urv_defs.v
View file @ 134759b2
......@@ -82,10 +82,7 @@
`define CSR_ID_MCAUSE 12'h342
`define CSR_ID_MIP 12'h344
`define CSR_ID_MIE 12'h304
`define CSR_ID_DBGSTATUS 12'h7c0
`define CSR_ID_DBGSCRATCH 12'h7c4
`define CSR_ID_DBGMBXI 12'h7d0
`define CSR_ID_DBGMBXO 12'h7d4
`define CSR_ID_DBGMBX 12'h7d0
`define CSR_OP_CSRRW 3'b001
`define CSR_OP_CSRRS 3'b010
......
rtl/urv_exec.v
View file @ 134759b2
......@@ -108,12 +108,9 @@ module urv_exec
input timer_tick_i,
// Debug mailboxes.
input [31:0] dbg_mbxi_data_i,
input dbg_mbxi_write_i,
output dbg_mbxi_full_o,
output [31:0] dbg_mbxo_data_o,
input dbg_mbxo_read_i,
output dbg_mbxo_full_o
input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o
);
wire [31:0] rs1, rs2;
......@@ -179,12 +176,9 @@ module urv_exec
.csr_mepc_i(csr_mepc),
.csr_mcause_i(csr_mcause),
.dbg_mbxi_data_i(dbg_mbxi_data_i),
.dbg_mbxi_write_i(dbg_mbxi_write_i),
.dbg_mbxi_full_o(dbg_mbxi_full_o),
.dbg_mbxo_data_o(dbg_mbxo_data_o),
.dbg_mbxo_read_i(dbg_mbxo_read_i),
.dbg_mbxo_full_o(dbg_mbxo_full_o)
.dbg_mbx_data_i(dbg_mbx_data_i),
.dbg_mbx_write_i(dbg_mbx_write_i),
.dbg_mbx_data_o(dbg_mbx_data_o)
);
urv_exceptions exception_unit
......
rtl/urv_fetch.v
View file @ 134759b2
......@@ -46,6 +46,8 @@ module urv_fetch
input dbg_force_i,
output dbg_enabled_o,
input [31:0] dbg_insn_i,
input dbg_insn_set_i,
output dbg_insn_ready_o,
input x_dbg_toggle
);
......@@ -69,6 +71,7 @@ module urv_fetch
assign im_addr_o = pc_next;
assign dbg_enabled_o = dbg_mode;
assign dbg_insn_ready_o = pipeline_cnt == 4;
always@(posedge clk_i)
if (rst_i)
......@@ -120,7 +123,6 @@ module urv_fetch
// Leave debug mode immediately.
dbg_mode <= 0;
f_valid_o <= 0;
// pipeline_cnt must be 0.
end
else
begin
......@@ -128,6 +130,11 @@ module urv_fetch
f_ir_o <= dbg_insn_i;
f_valid_o <= 1;
end
if (x_dbg_toggle || dbg_insn_set_i)
pipeline_cnt <= 0;
else if (pipeline_cnt != 4)
pipeline_cnt <= pipeline_cnt + 1;
end
else if(im_valid_i)
begin
......@@ -136,7 +143,7 @@ module urv_fetch
f_valid_o <= (rst_d && !x_bra_i);
end
else
begin// if (i_valid_i)
begin
f_valid_o <= 0;
end
end
......
rtl/urv_writeback.v
View file @ 134759b2
......@@ -28,7 +28,6 @@ module urv_writeback
input clk_i,
input rst_i,
input w_stall_i,
output w_stall_req_o,
input [2:0] x_fun_i,
......@@ -113,14 +112,11 @@ module urv_writeback
rf_rd_value <= x_rd_value_i;
always@*
if (w_stall_i)
rf_rd_write <= 0;
else if (x_load_i && dm_load_done_i)
if (x_load_i && dm_load_done_i)
rf_rd_write <= x_valid_i;
else
rf_rd_write <= x_rd_write_i & x_valid_i;
assign rf_rd_write_o = rf_rd_write;
assign rf_rd_value_o = rf_rd_value;
assign rf_rd_o = x_rd_i;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment