remove dm_ready_i (was unused and not working).

rtl/urv_cpu.v

@@ -54,7 +54,6 @@ module urv_cpu
    output [31:0] dm_data_s_o,
    input [31:0]  dm_data_l_i,
    output [3:0]  dm_data_select_o,
-   input 	 dm_ready_i,
 
    output 	 dm_store_o,
    output 	 dm_load_o,
@@ -342,7 +341,6 @@ module urv_cpu
       .dm_data_select_o(dm_data_select_o),
       .dm_store_o(dm_store_o),
       .dm_load_o(dm_load_o),
-      .dm_ready_i(dm_ready_i),
 
       // CSR registers/timer stuff
       .csr_time_i(csr_time),

rtl/urv_exec.v

@@ -105,7 +105,6 @@ module urv_exec
    output [3:0]      dm_data_select_o,
    output 	     dm_store_o,
    output 	     dm_load_o,
-   input 	     dm_ready_i,
 
    input [39:0]      csr_time_i,
    input [39:0]      csr_cycles_i,
@@ -535,9 +534,6 @@ module urv_exec
        x_stall_req_o <= 0;
      else if(divider_stall_req || multiply_stall_req)
        x_stall_req_o <= 1;
-   // stall if memory request pending, but memory not ready
-     else if ((d_is_load_i || d_is_store_i) && d_valid_i && !x_kill_i && !dm_ready_i)
-       x_stall_req_o <= 1;
      else
        x_stall_req_o <= 0;
 

tb/isa-testsuite/main.sv

@@ -76,7 +76,6 @@ module ICpuTestWrapper
    wire        dm_store = dm_store_m[r_active_cpu];
    wire        dm_load = dm_load_m[r_active_cpu];
    reg 	       dm_valid_l = 1;
-   reg         dm_ready = 0;
 
    wire        dm_delay = configs[r_active_cpu].ws;
    wire        dm_store_done = dm_store_done_d[dm_delay];
@@ -186,7 +185,6 @@ module ICpuTestWrapper
         dm_store_done_d <= {dm_store_done_d[0], dm_store};
 
         //  Read data memory
-        dm_ready <= 1;
         dm_data_l_d[1] <= dm_data_l_d[0];
 	dm_data_l_d[0] <= dm_load ? mem[(dm_addr/4) % mem_size] : 'x;
         dm_load_done_d <= {dm_load_done_d[0], dm_load};
@@ -222,7 +220,6 @@ module ICpuTestWrapper
 	    .dm_load_o(dm_load_m[i]),
 	    .dm_store_done_i(dm_store_done),
 	    .dm_load_done_i(dm_load_done),
-            .dm_ready_i(dm_ready),
 
 	    // Debug
 	    .dbg_force_i(1'b0),