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urv-core
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5c7e906c
Commit
5c7e906c
authored
6 years ago
by
Tristan Gingold
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Update MIMPID.
parent
56af5885
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rtl/urv_csr.v
+1
-1
1 addition, 1 deletion
rtl/urv_csr.v
rtl/urv_defs.v
+1
-0
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rtl/urv_defs.v
with
2 additions
and
1 deletion
rtl/urv_csr.v
+
1
−
1
View file @
5c7e906c
...
...
@@ -88,7 +88,7 @@ module urv_csr
`CSR_ID_MIP
:
csr_in1
<=
csr_mip_i
;
`CSR_ID_MIE
:
csr_in1
<=
csr_mie_i
;
`CSR_ID_DBGMBX
:
csr_in1
<=
g_with_hw_debug
?
mbx_data
:
32'h0
;
`CSR_ID_MIMPID
:
csr_in1
<=
32'h201901
25
;
`CSR_ID_MIMPID
:
csr_in1
<=
32'h201901
31
;
default:
csr_in1
<=
32'h0
;
endcase
// case (d_csr_sel_i)
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...
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rtl/urv_defs.v
+
1
−
0
View file @
5c7e906c
...
...
@@ -93,6 +93,7 @@
/* History for MIMPID:
0000_0000: mimpid not implemented
2019_0125: mimpid added.
2019_0131: data memory wait state.
*/
`define
CSR_OP_CSRRW 3
'
b001
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