Remove unused signals, fix some warnings.

rtl/urv_cpu.v

@@ -108,16 +108,13 @@ module urv_cpu
    wire [4:0] 	 d2x_rs1;
    wire [4:0] 	 d2x_rs2;
    wire [4:0] 	 d2x_rd;
-   wire [4:0] 	 d2x_shamt;
    wire [2:0] 	 d2x_fun;
    wire [4:0] 	 d2x_opcode;
    wire 	 d2x_shifter_sign;
    wire 	 d2x_is_load, d2x_is_store, d2x_is_undef;
    wire [31:0] 	 d2x_imm;
-   wire 	 d2x_is_signed_compare;
    wire 	 d2x_is_signed_alu_op;
    wire 	 d2x_is_add_o;
-   wire 	 d2x_is_shift_o;
    wire [2:0] 	 d2x_rd_source;
    wire 	 d2x_rd_write;
    wire [11:0] 	 d2x_csr_sel;
@@ -204,14 +201,11 @@ module urv_cpu
       .x_rs2_o(d2x_rs2),
       .x_imm_o(d2x_imm),
       .x_rd_o(d2x_rd),
-      .x_shamt_o(d2x_shamt),
       .x_fun_o(d2x_fun),
       .x_opcode_o(d2x_opcode),
       .x_shifter_sign_o(d2x_shifter_sign),
-      .x_is_signed_compare_o(d2x_is_signed_compare),
       .x_is_signed_alu_op_o(d2x_is_signed_alu_op),
       .x_is_add_o(d2x_is_add),
-      .x_is_shift_o(d2x_is_shift),
       .x_is_load_o(d2x_is_load),
       .x_is_store_o(d2x_is_store),
       .x_is_undef_o(d2x_is_undef),
@@ -282,10 +276,8 @@ module urv_cpu
       .d_rd_i(d2x_rd),
       .d_fun_i(d2x_fun),
       .d_imm_i(d2x_imm),
-      .d_is_signed_compare_i(d2x_is_signed_compare),
       .d_is_signed_alu_op_i(d2x_is_signed_alu_op),
       .d_is_add_i(d2x_is_add),
-      .d_is_shift_i(d2x_is_shift),
       .d_is_load_i(d2x_is_load),
       .d_is_store_i(d2x_is_store),
       //.d_is_divide_i(1'b0),

rtl/urv_decode.v

@@ -49,14 +49,11 @@ module urv_decode
  output [4:0]      x_rs1_o,
  output [4:0]      x_rs2_o,
  output [4:0]      x_rd_o,
- output reg [4:0]  x_shamt_o,
  output reg [2:0]  x_fun_o,
  output [4:0]      x_opcode_o,
  output reg        x_shifter_sign_o,
- output reg        x_is_signed_compare_o,
  output reg        x_is_signed_alu_op_o,
  output reg        x_is_add_o,
- output            x_is_shift_o,
  output reg        x_is_load_o,
  output reg        x_is_store_o,
  output reg        x_is_undef_o,
@@ -161,8 +158,6 @@ module urv_decode
 	  x_rs2 <= f_rs2;
 	  x_rd <= f_rd;
 	  x_opcode <= d_opcode;
-
-	  x_shamt_o <= f_ir_i[24:20];
        end
 
    // ALU function decoding
@@ -326,7 +321,6 @@ module urv_decode
           x_is_ebreak_o <= (d_opcode == `OPC_SYSTEM) && (d_fun == 0) && (f_ir_i [31:20] == 12'b0000000_00001);
        end
 
-   assign x_is_shift_o = x_is_shift;
    assign x_rd_write_o = x_rd_write;
 
 endmodule // rv_decode

rtl/urv_defs.v

@@ -68,7 +68,7 @@
 `define RD_SOURCE_ALU 3'b000
 `define RD_SOURCE_SHIFTER 3'b010
 `define RD_SOURCE_MULTIPLY 3'b001
-`define RD_SOURCE_DIVIDE 3'b011
+//  `define RD_SOURCE_DIVIDE 3'b011 ?? conflict with CSR
 `define RD_SOURCE_CSR 3'b011
 
 //  CSR addresses

rtl/urv_exceptions.v

@@ -34,7 +34,6 @@ module urv_exceptions
    input         d_is_csr_i,
    input         d_is_mret_i,
 
-   input [2:0]   d_fun_i,
    input [4:0]   d_csr_imm_i,
    input [11:0]  d_csr_sel_i,
 
@@ -67,8 +66,6 @@ module urv_exceptions
 
    reg [3:0] 	 csr_mcause;
 
-   reg 		 exception;
-
    reg [5:0] 	 except_vec_masked;
 
    assign csr_mcause_o = {28'h0, csr_mcause};
@@ -97,10 +94,6 @@ module urv_exceptions
 	end
      end
 
-   always@*
-     exception <= |except_vec_masked | exp_invalid_insn_i;
-
-
    always@(posedge clk_i)
      if(rst_i)
        begin

rtl/urv_exec.v

@@ -55,10 +55,8 @@ module urv_exec
    input [11:0]      d_csr_sel_i,
 
    input [31:0]      d_imm_i,
-   input             d_is_signed_compare_i,
    input             d_is_signed_alu_op_i,
    input             d_is_add_i,
-   input             d_is_shift_i,
    input             d_is_load_i,
    input             d_is_store_i,
   // input 	     d_is_divide_i,
@@ -128,7 +126,8 @@ module urv_exec
 
    reg [31:0] 	 branch_target;
 
-   reg [31:0] 	 dm_addr, dm_data_s, dm_select_s;
+   reg [31:0]    dm_addr, dm_data_s;
+   reg [3:0]     dm_select_s;
 
    // Comparator
    wire [32:0] 	 cmp_op1 = { d_is_signed_alu_op_i ? rs1[31] : 1'b0, rs1 };
@@ -191,7 +190,6 @@ module urv_exec
 
       .d_is_csr_i(d_is_csr_i),
       .d_is_mret_i (d_is_mret_i),
-      .d_fun_i(d_fun_i),
       .d_csr_imm_i(d_csr_imm_i),
       .d_csr_sel_i(d_csr_sel_i),
       .x_csr_write_value_i(csr_write_value),
@@ -295,7 +293,6 @@ module urv_exec
       .d_shamt_i(alu_op2[4:0]),
       .d_fun_i(d_fun_i),
       .d_shifter_sign_i(d_shifter_sign_i),
-      .d_is_shift_i(d_is_shift_i),
 
       .w_rd_o(w_rd_shifter_o)
       );

rtl/urv_fetch.v

@@ -114,7 +114,7 @@ module urv_fetch
                          pipeline_cnt <= 0;
                       end
                     else
-                      pipeline_cnt <= pipeline_cnt + 1;
+                      pipeline_cnt <= pipeline_cnt + 1'b1;
                  end
                else if(dbg_mode)
                  begin
@@ -134,7 +134,7 @@ module urv_fetch
                     if (x_dbg_toggle || dbg_insn_set_i)
                       pipeline_cnt <= 0;
                     else if (pipeline_cnt != 4)
-                      pipeline_cnt <= pipeline_cnt + 1;
+                      pipeline_cnt <= pipeline_cnt + 1'b1;
                  end
                else if(im_valid_i)
                  begin

rtl/urv_shifter.v

@@ -42,8 +42,7 @@ module urv_shifter
 
      input [4:0]       d_shamt_i,
      input [2:0]       d_fun_i,
-     input 	       d_shifter_sign_i,
-     input 	       d_is_shift_i
+     input 	       d_shifter_sign_i
    );
 
    wire 	 extend_sign = ((d_fun_i == `FUNC_SR) && d_shifter_sign_i) ? d_rs1_i[31] : 1'b0;