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REVB production: mounting of some components does not look as expected.
#1
· opened
Jan 17, 2018
by
Dietrich Beck
bug
CLOSED
1
updated
Feb 12, 2019
REVB mechanics: USB connectors JTAGCON1 und USBCON1
#2
· opened
Jan 17, 2018
by
Dietrich Beck
bug
CLOSED
1
updated
Feb 12, 2019
PCI pins pullued up during FPGA boot
#5
· opened
May 03, 2017
by
Dusan Slavinec
bug
CLOSED
1
updated
Feb 12, 2019
IO CLK hangs?
#7
· opened
Mar 24, 2016
by
Piotr Miedzik
bug
CLOSED
2
updated
Feb 12, 2019
IO random peaks
#8
· opened
Mar 24, 2016
by
Piotr Miedzik
bug
CLOSED
2
updated
Feb 12, 2019
IO activity leds
#9
· opened
Feb 29, 2016
by
A. Hahn
bug
CLOSED
8
updated
Feb 12, 2019
biderectional buffers inappropriate
#14
· opened
Feb 23, 2016
by
Dietrich Beck
bug
CLOSED
2
updated
Feb 12, 2019
PCI Output signals does not meet Timing Parameters
#15
· opened
Feb 18, 2016
by
Piotr Miedzik
bug
CLOSED
2
updated
Feb 12, 2019
PCI bridge randomly does not response to master
#16
· opened
Feb 18, 2016
by
Piotr Miedzik
bug
CLOSED
8
updated
Feb 12, 2019
errors when initializing BAR 0
#17
· opened
Feb 16, 2016
by
Piotr Miedzik
bug
CLOSED
5
updated
Feb 12, 2019
PC does not boot
#21
· opened
Feb 12, 2016
by
Piotr Miedzik
bug
CLOSED
4
updated
Feb 12, 2019