White Rabbit Timing Receiver in PMC Format
Project Description
A White Rabbit Timing Receiver in PMC (PCI Mezzanine Card) format.
Main Features
- FPGA
- Altera Arria V GX (5AGXMA3D4F27I3N)
- CPLD
- Xilinx Coolrunner-II (XC2C64A)
- Miscellaneous
- On-board thermometer IC (DS18B20U+)
- Unique 64-bit identifier (DS18B20U+)
- Front panel
- 1x SFP port (White Rabbit compatible)
- 5x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
- 6x Programmable LEDs
Project Information
- Design files
- FPGA source code
- Hardware commissioning guide
- Description of the General Machine Timing System (GMT) @ GSI.
- Description of Timing Receivers for the GMT.
Contacts
Commercial Producers
- Cosylab, Slovenia
General Question About the Project
- Alexander Hahn - GSI, Germany
FPGA Gateware
git clone https://github.com/GSI-CS-CO/bel_projects.git
README.md => See "Build Gateware(s)"
Status
| Date | Event |
|---|---|
| 05-05-2014 | First specification written |
| 23-01-2015 | Created project and repository on OHWR |
| 11-02-2015 | Schematics done |
| 17-08-2015 | PCB Layout done |
| 01-10-2015 | Design prototype is done |
| 15-01-2016 | GSI received the first prototype |
| 09-04-2018 | GSI received REVB |
| 12-12-2018 | REVC (FoS) delivered to GSI |
| 01-03-2019 | GSI approved FoS |
| 01-04-2019 | Released! |
| 01-05-2019 | Cosylab produced 220 devices for GSI |