Commits · 1.2.1 · Projects / TimEX3 · Open Hardware Repository

17 Jun, 2013 1 commit

VHDL : Compensated output offsets in duplication mode · 5182c64f

Jean-Paul Ricaud authored Jun 17, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	new file:   fpga/TimEX3/keep.ncd
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl

5182c64f

12 Jun, 2013 1 commit

VHDL : added a reset impulse on rising edge of pre top-up signal to · b523d04e

Jean-Paul Ricaud authored Jun 12, 2013

reset the beam lost cycle ; cleaned comments and signal names

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

b523d04e

30 Apr, 2013 1 commit

VHDL : corrected comments of the top-up gating · b5fc43b9

Jean-Paul Ricaud authored Apr 30, 2013

 On branch development

	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/top.vhdl

b5fc43b9

26 Apr, 2013 2 commits

VHDL : updated the topup_config.txt file to reflect the new outputs · 00d1ee91
Jean-Paul Ricaud authored Apr 26, 2013
```
configuration

 On branch development

	modified:   fpga/sources/src_topup/topup_config.txt
```
00d1ee91

VHDL : added beam lost monitoring. In top-up gating mode, the outputs of · 3cf46b9a

Jean-Paul Ricaud authored Apr 26, 2013

the board are now configured as :

output(2) : negative gating window
output(3) : negative beam lost
output(4) : negative (beam lost + gating) window

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl

3cf46b9a

12 Apr, 2013 1 commit

VHDL : corrected a error in top-up gating module ; changed the · bfae43b6

Jean-Paul Ricaud authored Apr 12, 2013

monitoring to monitor and gate a beam lost

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	new file:   fpga/sources/src_topup/topup_injError.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	deleted:    fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

bfae43b6

09 Apr, 2013 1 commit

typo correction · c012f785

Jean-Paul Ricaud authored Apr 09, 2013

 On branch development

	modified:   fpga/sources/src_topup/topup_config.txt

c012f785

19 Mar, 2013 1 commit
- VHDL : adjusted the top-up holdoff value · a2e3bca4
  Jean-Paul Ricaud authored Mar 19, 2013
```
 On branch development

	modified:   fpga/sources/registers_init.vhdl
```
  a2e3bca4
18 Mar, 2013 1 commit

VHDL : added LINAC multi-pulse function · 69f29835

Jean-Paul Ricaud authored Mar 18, 2013

SCH : corrected typo error

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_config.txt
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_andpulses.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_config.txt
	new file:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_monitoring.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_top.vhdl
	modified:   fpga/sources/src_test/test_config.txt
	modified:   fpga/sources/src_topup/topup_config.txt
	modified:   fpga/sources/top.vhdl
	modified:   sch/Expansion_connectors.sch
	modified:   sch/FPGA.sch
	modified:   sch/FPGA_config.sch
	modified:   sch/Osc.sch
	modified:   sch/PCI9030.sch
	modified:   sch/cPCI_connector.sch
	modified:   sch/input.sch
	modified:   sch/outputs.sch
	modified:   sch/psu.sch
	modified:   sch/reset.sch
	modified:   sch/timex3_sch-cache.lib
	modified:   sch/timex3_sch.pro
	modified:   sch/timex3_sch.sch
	modified:   sch/top.sch

69f29835

14 Mar, 2013 1 commit

SCH : replaced C2 ; C 11 ; C12 C13 & C14 by 0R (better ligne adaptation) · 5fc0ff0a

Jean-Paul Ricaud authored Mar 14, 2013

 On branch development

	modified:   sch/Expansion_connectors.sch
	modified:   sch/FPGA.sch
	modified:   sch/FPGA_config.sch
	modified:   sch/Osc.sch
	modified:   sch/PCI9030.sch
	modified:   sch/bom_TTL.xlsx
	modified:   sch/cPCI_connector.sch
	modified:   sch/input.sch
	modified:   sch/outputs.sch
	modified:   sch/psu.sch
	modified:   sch/reset.sch
	modified:   sch/timex3_sch-cache.lib
	modified:   sch/timex3_sch.sch
	modified:   sch/top.sch

5fc0ff0a

13 Mar, 2013 1 commit

VHDL : changed the time base of duplication monitor to 1 ms ; added some · 0c5e42bb

Jean-Paul Ricaud authored Mar 13, 2013

signal to improve the skew
CAD : changed the names OUT1 -> OUT0 ; OUT2 -> OUT1 ; OUT3 -> OUT2 ;
OUT4 -> OUT3

 On branch development

	renamed:    cao/TimEX3_TTL-FP.dwg -> CAD/TimEX3_TTL-FP.dwg
	renamed:    cao/TimEX3_gating-FP.dwg -> CAD/TimEX3_gating-FP.dwg
	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/src_duplication/dup_duplication.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl

0c5e42bb

11 Mar, 2013 1 commit

VHDL : changed the time base to 1 kHz ; corrected an unconnected port ; · 96438d55

Jean-Paul Ricaud authored Mar 11, 2013

corrected an unreliable equality

 On branch development

	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/testbench/clk_sources_tb.vhdl
	modified:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/testbench/topup_gating_tb.vhdl
	modified:   fpga/sources/testbench/topup_monitor_tb.vhdl
	modified:   fpga/sources/top.vhdl

96438d55

07 Mar, 2013 1 commit

VHDL : corrected an error in addresses of the cPCI registers ; Added a · 1f60834a

Jean-Paul Ricaud authored Mar 07, 2013

file with initial value of registers

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	new file:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/top.vhdl

1f60834a

06 Mar, 2013 1 commit
- VHDL : corrected a error in top module ; added more comment on registers · 6f6643a7
  Jean-Paul Ricaud authored Mar 06, 2013
```
 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/top.vhdl
```
  6f6643a7
05 Mar, 2013 1 commit
- Added PLX9030 EEPROM binaries · 0722e3ec
  Jean-Paul Ricaud authored Mar 05, 2013
```
 On branch development

	new file:   cPCI/TIMEX3_PLX_EEPROM.eep
```
  0722e3ec
01 Mar, 2013 2 commits
- VHDL : added reset in sensibility list in clk_sources.vhdl ; switched to · 798f3542
  Jean-Paul Ricaud authored Mar 01, 2013
```
PlanAhead as it's what we should do

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/clk_sources.vhdl
```
  798f3542
- VHDL : coorected typo error in topup_top.vhdl · 60adf687
  Jean-Paul Ricaud authored Mar 01, 2013
```
 On branch development

	modified:   fpga/sources/src_topup/topup_top.vhdl
```
  60adf687
28 Feb, 2013 1 commit

VHDL : modified repertories names ; corrected clk source ; corrected · 01dec940

Jean-Paul Ricaud authored Feb 28, 2013

top-up monitoring

On branch development

modified: fpga/sources/clk_sources.vhdl
renamed: fpga/sources/cPCI/cPCI_hermes.vhdl -> fpga/sources/src_cPCI/cPCI_hermes.vhdl
renamed: fpga/sources/cPCI/cPCI_hermes_registers.vhdl -> fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
renamed: fpga/sources/cPCI/cPCI_statusManager.vhdl -> fpga/sources/src_cPCI/cPCI_statusManager.vhdl
renamed: fpga/sources/source_duplication/dup_config.txt -> fpga/sources/src_duplication/dup_config.txt
renamed: fpga/sources/source_duplication/dup_duplication.vhdl -> fpga/sources/src_duplication/dup_duplication.vhdl
renamed: fpga/sources/source_duplication/dup_leds.vhdl -> fpga/sources/src_duplication/dup_leds.vhdl
renamed: fpga/sources/source_duplication/dup_monitoring.vhdl -> fpga/sources/src_duplication/dup_monitoring.vhdl
renamed: fpga/sources/source_duplication/dup_top.vhdl -> fpga/sources/src_duplication/dup_top.vhdl
renamed: fpga/sources/test/test_config.txt -> fpga/sources/src_test/test_config.txt
renamed: fpga/sources/test/test_top.vhdl -> fpga/sources/src_test/test_top.vhdl
renamed: fpga/sources/source_topup/topup_config.txt -> fpga/sources/src_topup/topup_config.txt
renamed: fpga/sources/source_topup/topup_gating.vhdl -> fpga/sources/src_topup/topup_gating.vhdl
renamed: fpga/sources/source_topup/topup_leds.vhdl -> fpga/sources/src_topup/topup_leds.vhdl
renamed: fpga/sources/source_topup/topup_monitor.vhdl -> fpga/sources/src_topup/topup_monitor.vhdl
renamed: fpga/sources/source_topup/topup_top.vhdl -> fpga/sources/src_topup/topup_top.vhdl
modified: fpga/sources/top.vhdl

01dec940

27 Feb, 2013 1 commit
- VHDL : corrected a bad init value for missing signal · 944590f8
  Jean-Paul Ricaud authored Feb 27, 2013
```
 On branch development

	modified:   fpga/sources/source_duplication/dup_leds.vhdl
```
  944590f8
22 Feb, 2013 1 commit

VHDL : added a module for simple test of the proto ; added first FPGA's · 6aa07f2a

Jean-Paul Ricaud authored Feb 22, 2013

eeprom binaries

 On branch development

	new file:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/source_duplication/dup_config.txt
	new file:   fpga/sources/test/test_config.txt
	new file:   fpga/sources/test/test_top.vhdl
	modified:   fpga/sources/top.vhdl

6aa07f2a

05 Feb, 2013 1 commit

PCB : few adjustement on silk screens · 4260867e

Jean-Paul Ricaud authored Feb 05, 2013

PCB : added components position files

 On branch development

	new file:   pcb/fab/timex3_pcb_L1_TOP.pos
	new file:   pcb/fab/timex3_pcb_L6_BOTTOM.pos
	modified:   pcb/gerber/timex3_pcb-Comments.gbr
	modified:   pcb/gerber/timex3_pcb-Drawings.gbr
	modified:   pcb/gerber/timex3_pcb-L1_TOP.gtl
	modified:   pcb/gerber/timex3_pcb-L2_GND.gbr
	modified:   pcb/gerber/timex3_pcb-L3_SIG.gbr
	modified:   pcb/gerber/timex3_pcb-L4_5V.gbr
	modified:   pcb/gerber/timex3_pcb-L5_3V3.gbr
	modified:   pcb/gerber/timex3_pcb-L6_BOTTOM.gbl
	modified:   pcb/gerber/timex3_pcb-Mask_Back.gbs
	modified:   pcb/gerber/timex3_pcb-Mask_Front.gts
	modified:   pcb/gerber/timex3_pcb-PCB_Edges.gbr
	modified:   pcb/gerber/timex3_pcb-SilkS_Back.gbo
	modified:   pcb/gerber/timex3_pcb-SilkS_Front.gto
	modified:   pcb/gerber/timex3_pcb-SoldP_Back.gbp
	modified:   pcb/gerber/timex3_pcb-SoldP_Front.gtp
	modified:   pcb/timex3_pcb.brd
	modified:   sch/timex3_sch.pro

4260867e

24 Jan, 2013 1 commit

PCB : added fiducial · 79a4ea2f

Jean-Paul Ricaud authored Jan 24, 2013

 On branch development

	modified:   pcb/gerber/timex3_pcb-Comments.gbr
	modified:   pcb/gerber/timex3_pcb-Drawings.gbr
	modified:   pcb/gerber/timex3_pcb-L1_TOP.gtl
	modified:   pcb/gerber/timex3_pcb-L2_GND.gbr
	modified:   pcb/gerber/timex3_pcb-L3_SIG.gbr
	modified:   pcb/gerber/timex3_pcb-L4_5V.gbr
	modified:   pcb/gerber/timex3_pcb-L5_3V3.gbr
	modified:   pcb/gerber/timex3_pcb-L6_BOTTOM.gbl
	modified:   pcb/gerber/timex3_pcb-Mask_Back.gbs
	modified:   pcb/gerber/timex3_pcb-Mask_Front.gts
	modified:   pcb/gerber/timex3_pcb-PCB_Edges.gbr
	modified:   pcb/gerber/timex3_pcb-SilkS_Back.gbo
	modified:   pcb/gerber/timex3_pcb-SilkS_Front.gto
	modified:   pcb/gerber/timex3_pcb-SoldP_Back.gbp
	modified:   pcb/gerber/timex3_pcb-SoldP_Front.gtp
	modified:   pcb/timex3_pcb.brd

79a4ea2f

09 Jan, 2013 1 commit

VHDL : Some works to make HERMES module more abstract · c4617c06

Jean-Paul Ricaud authored Jan 09, 2013

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_monitor.vhdl
	modified:   fpga/sources/top.vhdl

c4617c06

18 Dec, 2012 2 commits

VHDL : minor typo corrections before holidays · 6dff6ba0

Jean-Paul Ricaud authored Dec 18, 2012

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/top.vhdl

6dff6ba0

VHDL : Added test benches for top-up gating ; added some comments in · 9a5d3030

Jean-Paul Ricaud authored Dec 18, 2012

files

 On branch development

	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_monitor.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	new file:   fpga/sources/testbench/topup_gating_tb.vhdl
	new file:   fpga/sources/testbench/topup_monitor_tb.vhdl

9a5d3030

17 Dec, 2012 1 commit

VHDL : added hold off and width delays for the top-up gating · ce8085d8

Jean-Paul Ricaud authored Dec 17, 2012

 On branch development

	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_monitor.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

ce8085d8

14 Dec, 2012 1 commit

VHDL : After discussion with SMIS beam line, start adding a user defined · 27e1e29a

Jean-Paul Ricaud authored Dec 14, 2012

hold off and gating windows width delays => to be done

 On branch development

	modified:   fpga/sources/source_topup/topup_gating.vhdl
	new file:   fpga/sources/source_topup/topup_monitor.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

27e1e29a

05 Dec, 2012 1 commit

VHDL : added user adjustable delays for pre / post top-up missing · 5ec57999

Jean-Paul Ricaud authored Dec 05, 2012

signals ; added a status register

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	new file:   fpga/sources/cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

5ec57999

04 Dec, 2012 1 commit

VHDL : cleaned up HERMES module to make a more stand_alone module (still · e1a1d779

Jean-Paul Ricaud authored Dec 04, 2012

can be improved...).
VHDL : added a user adjustable delay for synchro pulse missing (todo :
report the missing signal in the status register).
VHDL : little code clean up.
BOM  : added pdf of the BOM.

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_duplication/dup_top.vhdl
	modified:   fpga/sources/top.vhdl
	modified:   sch/bom_TTL.xlsx

e1a1d779

20 Nov, 2012 1 commit

Added config file for duplication and top-up gating otions · bd2eee9c

Jean-Paul Ricaud authored Nov 20, 2012

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	new file:   fpga/sources/source_duplication/dup_config.txt
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_duplication/dup_monitoring.vhdl
	new file:   fpga/sources/source_topup/topup_config.txt
	modified:   fpga/sources/source_topup/topup_leds.vhdl

bd2eee9c

19 Nov, 2012 1 commit

SCH : corrected bad refrerance of J1 : 449.42.2522.207 => 449.42.2522.201 · 0c371bcb

Jean-Paul Ricaud authored Nov 19, 2012

BOM : corrected bad refrerance of J1 : 449.42.2522.207 => 449.42.2522.201
VHDL : minor cosmetic improvements

 On branch development

	modified:   fpga/sources/testbench/clk_sources_tb.vhdl
	modified:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/testbench/reset_tb.vhdl
	modified:   sch/bom_TTL.xlsx
	modified:   sch/input.sch

0c371bcb

09 Nov, 2012 1 commit

VHDL : added the top-up gating blocks ; some typo modifications on · 075efff3

Jean-Paul Ricaud authored Nov 09, 2012

others files

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/reset.vhdl
	modified:   fpga/sources/source_duplication/dup_duplication.vhdl
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	modified:   fpga/sources/source_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/source_duplication/dup_top.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	modified:   fpga/sources/testbench/clk_sources_tb.vhdl
	modified:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/top.vhdl

075efff3

07 Nov, 2012 1 commit

VHDL : added signal monitoring + LEDs management for signal duplication · 730b84cd

Jean-Paul Ricaud authored Nov 07, 2012

block

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/reset.vhdl
	deleted:    fpga/sources/source_duplication/dup_detect_front.vhdl
	modified:   fpga/sources/source_duplication/dup_duplication.vhdl
	deleted:    fpga/sources/source_duplication/dup_impulse_detection.vhdl
	modified:   fpga/sources/source_duplication/dup_leds.vhdl
	new file:   fpga/sources/source_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/source_duplication/dup_top.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	modified:   fpga/sources/testbench/clk_sources_tb.vhdl
	modified:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/testbench/reset_tb.vhdl
	modified:   fpga/sources/top.vhdl

730b84cd

06 Nov, 2012 1 commit

VHDL : some works on duplication and gating code · 0dfad248

Jean-Paul Ricaud authored Nov 06, 2012

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/source_duplication/dup_duplication.vhdl
	modified:   fpga/sources/source_duplication/dup_top.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	new file:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/testbench/reset_tb.vhdl
	modified:   fpga/sources/top.vhdl

0dfad248

05 Nov, 2012 1 commit

VHDL : addded clock and reset management unit · 31f8504a

Jean-Paul Ricaud authored Nov 05, 2012

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/clk_sources.vhdl
	renamed:    fpga/sources/top_outputmux.vhdl -> fpga/sources/outputmux.vhdl
	renamed:    fpga/sources/top_reset.vhdl -> fpga/sources/reset.vhdl
	modified:   fpga/sources/source_duplication/dup_duplication.vhdl
	modified:   fpga/sources/source_duplication/dup_top.vhdl
	modified:   fpga/sources/source_topup/topup_gating.vhdl
	modified:   fpga/sources/source_topup/topup_leds.vhdl
	modified:   fpga/sources/source_topup/topup_top.vhdl
	renamed:    fpga/sources/clk_sources_tb.vhdl -> fpga/sources/testbench/clk_sources_tb.vhdl
	new file:   fpga/sources/testbench/reset_tb.vhdl
	modified:   fpga/sources/top.vhdl

31f8504a

31 Oct, 2012 1 commit

VHDL : added frequency divider ; somewhat cleaned files copied from · 94fcfa53

Jean-Paul Ricaud authored Oct 31, 2012

others projects*

 On branch development

	modified:   fpga/sources/cPCI/cPCI_hermes.vhdl
	new file:   fpga/sources/clk_sources.vhdl
	new file:   fpga/sources/clk_sources_tb.vhdl
	modified:   fpga/sources/top.vhdl

94fcfa53

30 Oct, 2012 1 commit

VHDL : copied some files from others projects as start point ; fpga pins · f45ed67e

Jean-Paul Ricaud authored Oct 30, 2012

assignement made on the top.ucf file

 On branch development

	new file:   fpga/TimEX3/top.ucf
	new file:   fpga/sources/cPCI/cPCI_hermes.vhdl
	new file:   fpga/sources/cPCI/cPCI_hermes_registers.vhdl
	new file:   fpga/sources/source_duplication/dup_detect_front.vhdl
	new file:   fpga/sources/source_duplication/dup_duplication.vhdl
	new file:   fpga/sources/source_duplication/dup_impulse_detection.vhdl
	new file:   fpga/sources/source_duplication/dup_leds.vhdl
	new file:   fpga/sources/source_duplication/dup_top.vhdl
	new file:   fpga/sources/source_topup/topup_gating.vhdl
	new file:   fpga/sources/source_topup/topup_leds.vhdl
	new file:   fpga/sources/source_topup/topup_top.vhdl
	new file:   fpga/sources/top.vhdl
	new file:   fpga/sources/top_outputmux.vhdl
	new file:   fpga/sources/top_reset.vhdl
	modified:   readme.txt

f45ed67e

26 Oct, 2012 2 commits

Added licences · 29fd51c3

Jean-Paul Ricaud authored Oct 26, 2012

 On branch development

	new file:   licenses/CERN-OHL-v1.1.txt
	new file:   licenses/lgpl-3.0.txt
	modified:   sch/bom_TTL.xlsx

29fd51c3

PCB : some more improvements · c7088a9c

Jean-Paul Ricaud authored Oct 26, 2012

 On branch development

	modified:   pcb/gerber/timex3_pcb-Comments.gbr
	modified:   pcb/gerber/timex3_pcb-Drawings.gbr
	modified:   pcb/gerber/timex3_pcb-L1_TOP.gtl
	modified:   pcb/gerber/timex3_pcb-L2_GND.gbr
	modified:   pcb/gerber/timex3_pcb-L3_SIG.gbr
	modified:   pcb/gerber/timex3_pcb-L4_5V.gbr
	modified:   pcb/gerber/timex3_pcb-L5_3V3.gbr
	modified:   pcb/gerber/timex3_pcb-L6_BOTTOM.gbl
	modified:   pcb/gerber/timex3_pcb-Mask_Back.gbs
	modified:   pcb/gerber/timex3_pcb-Mask_Front.gts
	modified:   pcb/gerber/timex3_pcb-NPTH-drl.pho
	modified:   pcb/gerber/timex3_pcb-NPTH.drl
	modified:   pcb/gerber/timex3_pcb-PCB_Edges.gbr
	modified:   pcb/gerber/timex3_pcb-SilkS_Back.gbo
	modified:   pcb/gerber/timex3_pcb-SilkS_Front.gto
	modified:   pcb/gerber/timex3_pcb-SoldP_Back.gbp
	modified:   pcb/gerber/timex3_pcb-SoldP_Front.gtp
	modified:   pcb/gerber/timex3_pcb-drl.pho
	modified:   pcb/gerber/timex3_pcb-drl.rpt
	modified:   pcb/gerber/timex3_pcb.drl
	modified:   pcb/timex3_pcb.brd

c7088a9c

25 Oct, 2012 1 commit

PCB : some minor improvement · 48549141

Jean-Paul Ricaud authored Oct 25, 2012

 On branch development

	modified:   pcb/gerber/timex3_pcb-Comments.gbr
	modified:   pcb/gerber/timex3_pcb-Drawings.gbr
	modified:   pcb/gerber/timex3_pcb-L1_TOP.gtl
	modified:   pcb/gerber/timex3_pcb-L2_GND.gbr
	modified:   pcb/gerber/timex3_pcb-L3_SIG.gbr
	modified:   pcb/gerber/timex3_pcb-L4_5V.gbr
	modified:   pcb/gerber/timex3_pcb-L5_3V3.gbr
	modified:   pcb/gerber/timex3_pcb-L6_BOTTOM.gbl
	modified:   pcb/gerber/timex3_pcb-Mask_Back.gbs
	modified:   pcb/gerber/timex3_pcb-Mask_Front.gts
	modified:   pcb/gerber/timex3_pcb-NPTH-drl.pho
	modified:   pcb/gerber/timex3_pcb-NPTH.drl
	modified:   pcb/gerber/timex3_pcb-PCB_Edges.gbr
	modified:   pcb/gerber/timex3_pcb-SilkS_Back.gbo
	modified:   pcb/gerber/timex3_pcb-SilkS_Front.gto
	modified:   pcb/gerber/timex3_pcb-SoldP_Back.gbp
	modified:   pcb/gerber/timex3_pcb-SoldP_Front.gtp
	modified:   pcb/gerber/timex3_pcb-drl.pho
	modified:   pcb/gerber/timex3_pcb-drl.rpt
	modified:   pcb/gerber/timex3_pcb.drl
	modified:   pcb/timex3_pcb.brd

48549141