VHDL : copied some files from others projects as start point ; fpga pins

assignement made on the top.ucf file On branch development new file: fpga/TimEX3/top.ucf new file: fpga/sources/cPCI/cPCI_hermes.vhdl new file: fpga/sources/cPCI/cPCI_hermes_registers.vhdl new file: fpga/sources/source_duplication/dup_detect_front.vhdl new file: fpga/sources/source_duplication/dup_duplication.vhdl new file: fpga/sources/source_duplication/dup_impulse_detection.vhdl new file: fpga/sources/source_duplication/dup_leds.vhdl new file: fpga/sources/source_duplication/dup_top.vhdl new file: fpga/sources/source_topup/topup_gating.vhdl new file: fpga/sources/source_topup/topup_leds.vhdl new file: fpga/sources/source_topup/topup_top.vhdl new file: fpga/sources/top.vhdl new file: fpga/sources/top_outputmux.vhdl new file: fpga/sources/top_reset.vhdl modified: readme.txt

VHDL : copied some files from others projects as start point ; fpga pins
assignement made on the top.ucf file On branch development new file: fpga/TimEX3/top.ucf new file: fpga/sources/cPCI/cPCI_hermes.vhdl new file: fpga/sources/cPCI/cPCI_hermes_registers.vhdl new file: fpga/sources/source_duplication/dup_detect_front.vhdl new file: fpga/sources/source_duplication/dup_duplication.vhdl new file: fpga/sources/source_duplication/dup_impulse_detection.vhdl new file: fpga/sources/source_duplication/dup_leds.vhdl new file: fpga/sources/source_duplication/dup_top.vhdl new file: fpga/sources/source_topup/topup_gating.vhdl new file: fpga/sources/source_topup/topup_leds.vhdl new file: fpga/sources/source_topup/topup_top.vhdl new file: fpga/sources/top.vhdl new file: fpga/sources/top_outputmux.vhdl new file: fpga/sources/top_reset.vhdl modified: readme.txt
f45ed67e · Jean-Paul Ricaud · 29fd51c3 · f45ed67e · f45ed67e · f45ed67e
Commit f45ed67e authored Oct 30, 2012 by Jean-Paul Ricaud
15 changed files
--- a/fpga/TimEX3/top.ucf
+++ b/fpga/TimEX3/top.ucf
--- a/fpga/sources/cPCI/cPCI_hermes.vhdl
+++ b/fpga/sources/cPCI/cPCI_hermes.vhdl
--- a/fpga/sources/cPCI/cPCI_hermes_registers.vhdl
+++ b/fpga/sources/cPCI/cPCI_hermes_registers.vhdl
+--------------------------------------------------------------------------------
+-- Title   : Hermes registers definitions
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : definition of the cPCI registers
+--------------------------------------------------------------------------------
+-- File     : cPCI_hermes_registers.vhdl
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 30, 2012
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+package cPCI_hermes_registers is
+
+  ------------------------------------------------------------------------------
+  --Registers address
+  ------------------------------------------------------------------------------
+  constant c_ADD_BOARDID_REG  : std_logic_vector (9 downto 2) := "00000000"; -- board ID register
+  constant c_ADD_FIRMWARE_REG : std_logic_vector (9 downto 2) := "00000001"; -- firmware's version register
+  constant c_ADD_TEST_REG     : std_logic_vector (9 downto 2) := "00000010"; -- test register
+  constant c_ADD_STATUS_REG   : std_logic_vector (9 downto 2) := "00000011"; -- status register
+  constant c_ADD_CMD_REG      : std_logic_vector (9 downto 2) := "00000100"; -- commands register
+  constant c_ADD_REGISTER0    : std_logic_vector (9 downto 2) := "00000101"; -- register 0
+  constant c_ADD_REGISTER1    : std_logic_vector (9 downto 2) := "00000110"; -- register 1
+  constant c_ADD_REGISTER2    : std_logic_vector (9 downto 2) := "00000111"; -- register 2
+  constant c_ADD_REGISTER3    : std_logic_vector (9 downto 2) := "00001000"; -- register 3
+  constant c_ADD_REGISTER4    : std_logic_vector (9 downto 2) := "00001101"; -- register 4
+  constant c_ADD_REGISTER5    : std_logic_vector (9 downto 2) := "00001110"; -- register 5
+  constant c_ADD_REGISTER6    : std_logic_vector (9 downto 2) := "00001111"; -- register 6
+  constant c_ADD_REGISTER7    : std_logic_vector (9 downto 2) := "00010000"; -- register 7
+  constant c_ADD_REGISTER8    : std_logic_vector (9 downto 2) := "00010001"; -- register 8
+  constant c_ADD_REGISTER9    : std_logic_vector (9 downto 2) := "00010010"; -- register 9
+  constant c_ADD_REGISTER10   : std_logic_vector (9 downto 2) := "00010011"; -- register 10
+  constant c_ADD_REGISTER11   : std_logic_vector (9 downto 2) := "00010100"; -- register 11
+  constant c_ADD_REGISTER12   : std_logic_vector (9 downto 2) := "00010101"; -- register 12
+  constant c_ADD_REGISTER13   : std_logic_vector (9 downto 2) := "00010110"; -- register 13
+  constant c_ADD_FOO_REG      : std_logic_vector (9 downto 2) := "00010111"; -- foo register, not used
+
+  constant c_BOARD_ID         : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
+  constant c_FIRMWARE_REV     : std_logic_vector (31 downto 0) := X"00000064"; -- firmware's version
+
+  ------------------------------------------------------------------------------
+  -- Registers
+  ------------------------------------------------------------------------------
+  signal s_TEST_REG   : std_logic_vector (31 downto 0); -- test register
+  signal s_STATUS_REG : std_logic_vector (31 downto 0); -- status register
+  signal s_CMD_REG    : std_logic_vector (31 downto 0); -- command register ; s_CSW = "000000000000001"
+  signal s_REGISTER0  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000000000010"
+  signal s_REGISTER1  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000000000010"
+  signal s_REGISTER2  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000000000100"
+  signal s_REGISTER3  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000000000100"
+  signal s_REGISTER4  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000000100000"
+  signal s_REGISTER5  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000001000000"
+  signal s_REGISTER6  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000010000000"
+  signal s_REGISTER7  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000000100000000"
+  signal s_REGISTER8  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000001000000000"
+  signal s_REGISTER9  : std_logic_vector (31 downto 0); -- register 0       ; s_CSW = "000010000000000"
+  signal s_REGISTER10 : std_logic_vector (31 downto 0); -- register 10      ; s_CSW = "000100000000000"
+  signal s_REGISTER11 : std_logic_vector (31 downto 0); -- register 11      ; s_CSW = "001000000000000"
+  signal s_REGISTER12 : std_logic_vector (31 downto 0); -- register 12      ; s_CSW = "010000000000000"
+  signal s_REGISTER13 : std_logic_vector (31 downto 0); -- register 13      ; s_CSW = "100000000000000"
+
+end package cPCI_hermes_registers;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+package body cPCI_hermes_registers is
+
+end package body cPCI_hermes_registers;
+
--- a/fpga/sources/source_duplication/dup_detect_front.vhdl
+++ b/fpga/sources/source_duplication/dup_detect_front.vhdl
+-------------------------------------------------------------------------------
+-- Title   : detecte front
+-- Project : La carte TimEX version 2
+-------------------------------------------------------------------------------
+-- File     : detect_front.vhd
+-- Revision : 1.0
+-- Created  : 06/07/2010
+-- Updated  :
+-------------------------------------------------------------------------------
+-- Author       : Joana
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        :
+-------------------------------------------------------------------------------
+-- Licence : Copyright 2008 - Synchrotron Soleil
+--           All rights reserved
+-------------------------------------------------------------------------------
+-- Description: Detecte les fronts montants sur l'entrée LVTTL
+-- Revision: 1.0
+-- Additional Comments:
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-------------------------------------------------------------------------------
+-----------------------------------ENTITY--------------------------------------
+-------------------------------------------------------------------------------
+
+ENTITY dup_detect_front IS
+  PORT (
+    Entree : IN  STD_LOGIC;
+    clk    : IN  STD_LOGIC;
+    frontM : OUT STD_LOGIC
+  );
+END dup_detect_front;
+
+-------------------------------------------------------------------------------
+---------------------------------ARCHITECTURE----------------------------------
+-------------------------------------------------------------------------------
+ARCHITECTURE archi_detect_front OF dup_detect_front IS
+
+  -- DECLARATION SIGNAL INTERNE
+  SIGNAL Q0,Q1,s_FrontM : std_logic := '0';   -- Bascules utilisées pour la
+                                              -- detection de front montant sur la clock 10Hz
+
+  BEGIN
+
+  -- DEBUT DU PROCESS
+  PROCESS(clk)
+  BEGIN
+    IF rising_edge (clk) THEN -- On utilise le signal 25MHz afin de detecter le mointre "mouvement" du signal.
+      Q0 <= Entree;           -- Valeur "passé" du signal
+      Q1 <= Q0;                -- Valeur "présent" du signal
+      IF Q0 = '1' AND Q1 = '0' THEN   -- On regarde s'il y a un front montant sur Entrée grâce a deux bascules
+        s_frontM <= '1';              -- Un front montant est détecté sur Entrée
+      ELSE
+        s_frontM <= '0';              -- Autre état du signal: totalement à '0', totalement à '1', en
+                                      -- front descendant
+      END IF;
+    END IF;
+  END PROCESS;
+  frontM <= s_frontM;                 -- Affectation de la valeur du signal interne s_frontM à la sortie
+                                      -- du bloc frontM
+END archi_detect_front;
+
--- a/fpga/sources/source_duplication/dup_duplication.vhdl
+++ b/fpga/sources/source_duplication/dup_duplication.vhdl
+-------------------------------------------------------------------------------
+-- Title   : Duplication
+-- Project : TimEX3
+-------------------------------------------------------------------------------
+-- Description : Signal duplication
+-------------------------------------------------------------------------------
+-- File     : duplication.vhd
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+-------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+-------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Modifications :
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+-----------------------------------ENTITY--------------------------------------
+-------------------------------------------------------------------------------
+
+entity dup_duplication is
+  port (
+    TTL   : in  std_logic;  -- Signal d'entre  dupliquer
+    TTL1  : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    TTL2  : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    TTL3  : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    TTL4  : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    PECL1 : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    PECL2 : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    PECL3 : out std_logic;  -- Signaul dupliqu pour duplication TTL
+    PECL4 : out std_logic   -- Signaul dupliqu pour duplication TTL
+  );
+END dup_duplication;
+
+-------------------------------------------------------------------------------
+---------------------------------ARCHITECTURE----------------------------------
+-------------------------------------------------------------------------------
+
+architecture archi_duplication of dup_duplication is
+
+begin
+
+  --PROCESS
+  --BEGIN
+   TTL1  <= TTL; --Liaison du signal d'entre  une sortie
+   TTL2  <= TTL; --Liaison du signal d'entre  une sortie
+   TTL3  <= TTL; --Liaison du signal d'entre  une sortie
+   TTL4  <= TTL; --Liaison du signal d'entre  une sortie
+
+   --PECL1 <= TTL; --Liaison du signal d'entre  une sortie
+   --PECL2 <= TTL; --Liaison du signal d'entre  une sortie
+   --PECL3 <= TTL; --Liaison du signal d'entre  une sortie
+   --PECL4 <= TTL; --Liaison du signal d'entre  une sortie
+   PECL1 <= '0';
+   PECL2 <= '0';
+   PECL3 <= '0';
+   PECL4 <= '0';
+  --END PROCESS;
+end archi_duplication;
+
--- a/fpga/sources/source_duplication/dup_impulse_detection.vhdl
+++ b/fpga/sources/source_duplication/dup_impulse_detection.vhdl
+-------------------------------------------------------------------------------
+-- Title   : Impulse Detection
+-- Project : Beam lines synchronization - TimBeL Mother Board 
+-------------------------------------------------------------------------------
+-- File     : impulse_detection.vhd
+-- Revision : 1.0
+-- Created  : 06/07/2010
+-- Updated  : 
+-------------------------------------------------------------------------------
+-- Author       : Joana
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : 
+-------------------------------------------------------------------------------
+-- Licence : Copyright 2010 - Synchrotron Soleil
+--           All rights reserved
+-------------------------------------------------------------------------------
+-- Description: Le bloc detection d'impulsion va nous servir à controler les LEDs 
+--            En même temps il va contrôle s'il y à du signal en entrée du FPGA
+--                 __         __               __
+--            IN: |  |____________|  |_____________|  |_______________________X...
+--                 _____________________________________________
+--            OUT:  |                              |______________...
+--
+--            Si au bout d'un moment nous n'avons plus aucun signal en entrée 
+--            La sortie pulse va être mise à '0' pour ne pas la laissé dans 
+--            l'état précedent au cas où elle serait à '1'
+--            Cette fonction est faite à l'aide d'un compteur et des detecteur de 
+--            front montant.
+-- Revision: 1.0
+-- Additional Comments: 
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-------------------------------------------------------------------------------
+-----------------------------------ENTITY--------------------------------------
+-------------------------------------------------------------------------------
+
+ENTITY dup_impulse_detection IS
+  Port (  
+    LVTTL     : IN  STD_LOGIC;  -- Entrée LVTTL
+    clk_10Hz  : IN  STD_LOGIC;  -- Horloge 10Hz
+    clk_25MHz : IN  STD_LOGIC;  -- Horloge 25MHz
+    pulse     : OUT STD_LOGIC   -- Sortie de la détection d'impulsion
+  );
+END dup_impulse_detection;
+
+-------------------------------------------------------------------------------
+---------------------------------ARCHITECTURE----------------------------------
+-------------------------------------------------------------------------------
+
+ARCHITECTURE archi_impulse_detection OF dup_impulse_detection IS
+
+  --SIGNAUX INTERNES
+  SIGNAL compteur  : INTEGER RANGE 0 TO 5 := 0;  -- signal interne pour faire le compteur
+  SIGNAL s_RESET   : STD_LOGIC := '0';  -- signal de RESET: quand RESET est à '1' c'est 
+                                        -- qu'il y a un problème on recoit plus de signal en entrée
+  SIGNAL s_FrontM_LVTTL : STD_LOGIC;    -- donne l'état des front: quand front_montant_LVTTL est à '1',
+                                        -- c'est que le signal est passer de '0' à '1', soit detection
+                                        -- d'un front montant
+  SIGNAL s_FrontM_10Hz  : STD_LOGIC;    -- donne l'état des front: quand front_montant_10Hz est à '1',
+                                        -- c'est que le signal est passer de '0' à '1', soit detection
+                                        -- d'un front montant
+
+  -------------------------------------------------------------------------------------------
+  -- DECLARATION COMPONENT
+  -------------------------------------------------------------------------------------------
+  COMPONENT dup_detect_front IS   -- detecte front montant sur signal LVTTL
+    PORT(
+      Entree : IN  STD_LOGIC; -- signal que l'on doit annalyser
+      clk    : IN  STD_LOGIC; -- horloges de synchronisation
+      frontM : OUT STD_LOGIC  -- signal de sortie
+    );
+  END COMPONENT dup_detect_front;
+
+  -------------------------------------------------------------------------------------------
+  -------------------------------------------------------------------------------------------
+  BEGIN
+
+  detect_front_In : dup_detect_front PORT MAP (
+    Entree =>  LVTTL,         -- Affectation de l'entrée du component à l'entrée du bloc detection d'impulsion
+    clk    =>  clk_25MHz,     -- Affectation de l'horloge de synchronisation
+    frontM =>  s_FrontM_LVTTL -- Affectation de la sortie à un signal interne du bloc detection d'impulsion
+  );
+
+  detect_front_CLK10 :  dup_detect_front PORT MAP (
+    Entree => clk_10Hz,       -- Affectation de l'entrée du component à l'entrée du bloc detection d'impulsion
+    clk    => clk_25MHz,      -- Affectation de l'horloge de synchronisation
+    frontM => s_FrontM_10Hz   -- Affectation de la sortie à un signal interne du bloc detection d'impulsion
+  );
+    
+  -- DEBUT PROCESS POUR LE COMPTEUR
+  PROCESS (clk_25MHz)
+  BEGIN
+    IF (rising_edge (clk_25MHz)) THEN  -- Horloge de synchronisation, rising_edge
+      IF s_FrontM_LVTTL = '1' THEN     -- Détection d'un front montant en entrée LVTTL
+        compteur <= 0;                 -- Mise à zéro de la variable compteur
+        s_RESET <= '0';                -- Mise à zéro du signal s_RESET
+      ELSIF s_FrontM_10Hz = '1' THEN   -- Detection d'un front montant sur la clock 10Hz, début de comptage
+        IF compteur = 3 THEN           -- Vérification de la valeur de compteur
+          s_RESET <= '1';              -- Mise à un du signal s_RESET => valeur du compteur supérieur à trois
+        ELSE
+          compteur <= compteur + 1;    -- Dans tous les autres cas, on incrémente la variable compteur
+        END IF;
+      END IF;   
+    END IF;
+  END PROCESS;  
+  --FIN PROCESS
+
+  pulse <= NOT s_RESET;  -- Traitement la sortie pulse qui va allumer les LEDs 
+
+END archi_impulse_detection;
+
--- a/fpga/sources/source_duplication/dup_leds.vhdl
+++ b/fpga/sources/source_duplication/dup_leds.vhdl
+-------------------------------------------------------------------------------
+-- Title   : LEDs
+-- Project : La carte TimEX version 2
+-------------------------------------------------------------------------------
+-- File     : dup_leds.vhd
+-- Revision : 1.0
+-- Created  : 08/07/2010
+-- Updated  :
+-------------------------------------------------------------------------------
+-- Author       : Joana
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        :
+-------------------------------------------------------------------------------
+-- Licence : Copyright 2010 - Synchrotron Soleil
+--           All rights reserved
+-------------------------------------------------------------------------------
+-- Description:   La LED verte (LED_V) est allume lorsque la duplication a t effectue.
+--          La LED rouge (LED_R) est allum lorque l'on n'a plus de signal en entre.
+--            Le code de la LED rouge n'a pas encore t effectu.
+-- Revision: 1.0
+-- Additional Comments:
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-------------------------------------------------------------------------------
+-----------------------------------ENTITY--------------------------------------
+-------------------------------------------------------------------------------
+
+ENTITY dup_LEDs IS
+  PORT (
+    impulse  : IN  STD_LOGIC;
+    clk_25MHZ: IN  STD_LOGIC;
+    LED_R    : OUT STD_LOGIC;
+    LED_V    : OUT STD_LOGIC
+  );
+END dup_LEDs;
+
+-------------------------------------------------------------------------------
+---------------------------------ARCHITECTURE----------------------------------
+-------------------------------------------------------------------------------
+
+ARCHITECTURE archi_LEDs OF dup_LEDs IS
+
+  BEGIN
+
+  PROCESS (clk_25MHZ)
+  BEGIN
+    IF (rising_edge (clk_25MHZ)) THEN  -- Synchronisation sur l'horloge 25MHz
+      IF impulse = '1' THEN
+        LED_R <= '0';                 -- Et la LED_R est teinte '0'
+      ELSE
+        LED_R <= '1';                 -- Et la LED_R s'allume
+      END IF;
+    END IF;
+  END PROCESS;
+
+  LED_V <= '1';                 -- A chaque impulsion la LED_V est allume '1'
+
+END archi_LEDs;
+
--- a/fpga/sources/source_duplication/dup_top.vhdl
+++ b/fpga/sources/source_duplication/dup_top.vhdl
+--------------------------------------------------------------------------------
+-- Title   : Top - duplication function
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : Top sheet of the duplication block
+--------------------------------------------------------------------------------
+-- File     : dup_top.vhd
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+entity dup_top is
+  port (
+    dup_inTTL    : in  std_logic; -- input TTL
+    dup_outTTL   : out std_logic_vector (4 downto 0); -- sortie , double implmentation
+    dup_outPECL  : out std_logic_vector (4 downto 0); -- sortie , double implmentation
+
+    -- EXTERNAL CLOCKS
+    dup_CLK25MHz : IN  STD_LOGIC; -- horloge de 25MHz
+    dup_CLK10Hz  : IN  STD_LOGIC; -- horloge de 10 Hz
+
+    -- command of the LEDs
+    -- LED 0 = rouge , 1 = vert
+    dup_LED      : out std_logic_vector (1 downto 0) -- variable de controle de la LED rouge
+  );
+end entity dup_top;
+
+--------------------------------------------------------------------------------
+---------------------------------ARCHITECTURE-----------------------------------
+--------------------------------------------------------------------------------
+ARCHITECTURE rtl_dupli of dup_top is
+
+  signal s_impulse : std_logic; -- detection of impulse
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-----------------------------DECLARATION COMPONENT------------------------------
+--------------------------------------------------------------------------------
+  -- Bloc de duplication du signal d'entre
+  component dup_duplication is
+    port (
+      TTL   : in  std_logic; -- Signal d'entre : c'est un signal LVTTL
+      TTL1  : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en TTL
+      TTL2  : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en TTL
+      TTL3  : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en TTL
+      TTL4  : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en TTL
+      PECL1 : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en LVPECL
+      PECL2 : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en LVPECL
+      PECL3 : out std_logic; -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en LVPECL
+      PECL4 : out std_logic  -- Signal de sortie  : c'est un signal LVTTL qui va servir  la conversion en LVPECL
+    );
+  end component dup_duplication;
+
+  -- Bloc de detection d'impulsion sur l'entre, il sert aussi  contrler les LEDs de signalisation
+  component dup_impulse_detection is
+    port (
+      LVTTL     : in  std_logic; -- Entre sur laquelle on detecte une impulsion
+      clk_10Hz  : in  std_logic; -- Entre de l'horloge 10Hz
+      clk_25MHz : in  std_logic; -- Entre de l'horloge 25MHz
+      pulse     : out std_logic  -- Sortie dtection d'impulsion
+    );
+  end component dup_impulse_detection;
+
+  -- Bloc de contrle des LEDs de signalisation
+  component dup_LEDs is
+    port (
+      impulse   : in  std_logic;  -- Entre relie  la sortie du bloc de detection d'impulsion
+      clk_25MHZ : in  std_logic; -- Entre de l'horloge 25MHz
+      LED_R     : out std_logic; -- Sortie qui contrle la LED rouge
+      LED_V     : out std_logic  -- Sortie qui contrle la LED verte
+    );
+  end component dup_LEDs;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+begin
+--------------------------------------------------------------------------------
+-----------------------------AFFECTATION COMPONENT------------------------------
+--------------------------------------------------------------------------------
+  Dupli : dup_duplication port map (
+    TTL     => dup_inTTL,      -- Entre TTL_in affecte  la pin in_LVTTL
+    TTL1    => dup_outTTL(1),  -- Sortie TTL1_out affecte  la pin in_TTL1
+    TTL2    => dup_outTTL(2),  -- Sortie TTL2_out affecte  la pin in_TTL2
+    TTL3    => dup_outTTL(3),  -- Sortie TTL3_out affecte  la pin in_TTL3
+    TTL4    => dup_outTTL(4),  -- Sortie TTL4_out affecte  la pin in_TTL4
+    PECL1   => dup_outPECL(1), -- Sortie PECL1_out affecte  la pin in_LVPECL1
+    PECL2   => dup_outPECL(2), -- Sortie PECL2_out affecte  la pin in_LVPECL2
+    PECL3   => dup_outPECL(3), -- Sortie PECL3_out affecte  la pin in_LVPECL3
+    PECL4   => dup_outPECL(4)  -- Sortie PECL4_out affecte  la pin in_LVPECL4
+  );
+
+  Impulse_detect: dup_impulse_detection port map (
+    LVTTL     => dup_inTTL,    -- Entre TTL_in affecte  la pin in_LVTTL
+    clk_10Hz  => dup_CLK10Hz,  -- Entre clk_10Hz affecte au signal in_CLK10Hz
+    clk_25MHz => dup_CLK25MHz, -- Entre clk_25MHz affecte au signal dup_CLK25MHz
+    pulse     => s_impulse   -- Sortie pulse affecte au signal interne s_impulse
+  );
+
+  LED : dup_LEDs  port map (
+    impulse   => s_impulse,  -- Entre impulse affecte au signal interne s_impulse
+    clk_25MHZ => dup_CLK25MHz, -- Entre clk_25MHz affecte au signal dup_CLK25MHz
+    LED_R     => dup_LED(0),     -- Sortie LED_R affecte au pin in_LEDr
+    LED_V     => dup_LED(1)      -- Sortie LED_V affecte au pin in_LEDv
+  );
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+  dup_outTTL(0)  <= '0';
+  dup_outPECL(0) <= '0';
+
+end architecture rtl_dupli;
--- a/fpga/sources/source_topup/topup_gating.vhdl
+++ b/fpga/sources/source_topup/topup_gating.vhdl
+-------------------------------------------------------------------------------
+-- Title   : Top-up gating
+-- Project : TimEX3
+-------------------------------------------------------------------------------
+-- Description : Gating of top-up
+--               Pre top-up  => s_set signal is set with input (0)
+--               Post top-up => s_set signal is reset with input (1)
+-------------------------------------------------------------------------------
+-- File     : topup_gating.vhdl
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+-------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+-------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Modifications :
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+--------------------------------- ENTITY --------------------------------------
+-------------------------------------------------------------------------------
+entity topup_gating is
+  port (
+    CLK25MHz   : in  std_logic;
+    CLK10Hz    : in  std_logic;
+    inTTL      : in  std_logic_vector (1 downto 0);
+    outTTL     : out std_logic_vector (4 downto 0);
+    outPECL    : out std_logic_vector (4 downto 0);
+    LEDstate   : out std_logic;
+    topupError : out std_logic
+  );
+end entity topup_gating ;
+
+-------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE ----------------------------------
+-------------------------------------------------------------------------------
+architecture rtl_topup_gating of topup_gating is
+  -----------------------------------------------------------------------------
+  -- constant
+  -----------------------------------------------------------------------------
+  constant c_CNTsetMAX   : std_logic_vector (15 downto 0) := X"2328"; -- 15mn
+  constant c_CNTresetMAX : std_logic_vector (11 downto 0) := X"4B0";  -- 2mn
+
+  -----------------------------------------------------------------------------
+  -- signal
+  -----------------------------------------------------------------------------
+  signal s_set        : std_logic;
+  signal s_CNTset     : std_logic_vector (15 downto 0);
+  signal s_CNTreset   : std_logic_vector (11 downto 0);
+  signal s_errorSet   : std_logic;
+  signal s_errorReset : std_logic;
+  signal s_topupError : std_logic;
+
+  -----------------------------------------------------------------------------
+  -- Components
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  --------------------------------- Main --------------------------------------
+  -----------------------------------------------------------------------------
+  begin
+
+   -- Set process
+   -- inTTL(0) = pre top-up ; inTTL(1) = post top-up
+  process (inTTL(1), inTTL(0))
+  begin
+    if (inTTL(1) = '1') then
+      s_set <= '0';
+    elsif (rising_edge(inTTL(0))) then
+      s_set <= '1';
+    else
+      s_set <= s_set;
+    end if;
+  end process;
+
+  -- Time out
+  process (CLK10Hz)
+  begin
+    if (rising_edge(CLK10Hz)) then
+      if ((s_set = '0') and (s_errorSet = '0')) then
+        s_CNTset   <= s_CNTset + 1;
+        s_CNTreset <= (others => '0');
+      end if;
+      if ((s_set = '1') and (s_errorReset = '0')) then
+        s_CNTreset <= s_CNTreset + 1;
+        s_CNTset   <= (others =>'0');
+      end if;
+    end if;
+  end process;
+
+  -- Error detection
+  process (CLK10Hz)
+  begin
+    if (rising_edge(CLK10Hz)) then
+      if (s_CNTset > c_CNTsetMax) then
+        s_errorSet <= '1';
+      else
+        s_errorSet <= '0';
+      end if;
+      if (s_CNTreset > c_CNTresetMax) then
+        s_errorReset <= '1';
+      else
+        s_errorReset <= '0';
+      end if;
+    end if;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  s_topupError <= s_errorSet or s_errorReset;
+  topupError   <= s_topupError;
+  outTTL  (1 downto 0) <= "00"; -- not used
+  outTTL  (4 downto 2) <= s_topupError & s_set & (not s_set);
+  outPECL (4 downto 0) <= "00000";
+  LEDstate             <= s_set;
+
+end architecture rtl_topup_gating;
+
--- a/fpga/sources/source_topup/topup_leds.vhdl
+++ b/fpga/sources/source_topup/topup_leds.vhdl
+-------------------------------------------------------------------------------
+-- Title   : Top-up LEDs
+-- Project : TimEX3
+-------------------------------------------------------------------------------
+-- Description : LEDs manager
+--               Green LED on = board OK ; green LED blincking =
+--                              board OK and injection is occuring
+--               Red LED on = error (pre top-up or post top-up missing)
+-------------------------------------------------------------------------------
+-- File     : topup_gating.vhdl
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+-------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+-------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Modifications :
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+--------------------------------- ENTITY --------------------------------------
+-------------------------------------------------------------------------------
+entity topup_leds is
+  port (
+    CLK10Hz    : in  std_logic;
+    LEDstate   : in  std_logic;
+    topupError : in  std_logic;
+    LEDout     : out std_logic_vector (1 downto 0)
+  );
+end entity topup_leds ;
+
+-------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE ----------------------------------
+-------------------------------------------------------------------------------
+architecture rtl_topup_leds of topup_leds is
+  -----------------------------------------------------------------------------
+  -- constant
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  -- signal
+  -----------------------------------------------------------------------------
+  signal s_LEDinj : std_logic;
+
+  -----------------------------------------------------------------------------
+  -- Components
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  --------------------------------- Main --------------------------------------
+  -----------------------------------------------------------------------------
+  begin
+
+  process (CLK10Hz)
+  begin
+    if (rising_edge(CLK10Hz)) then
+      if (LEDstate = '1') then
+        s_LEDinj <= not s_LEDinj;  -- Injection occuring
+      else
+        s_LEDinj <= '1';
+      end if;
+    end if;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  LEDout(0) <= topupError; -- Red LED
+  LEDout(1) <= s_LEDinj;   -- Green LED
+
+end architecture rtl_topup_leds;
+
--- a/fpga/sources/source_topup/topup_top.vhdl
+++ b/fpga/sources/source_topup/topup_top.vhdl
+--------------------------------------------------------------------------------
+-- Title   : Top-up gating top file
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : Top-up gating top sheet block
+--------------------------------------------------------------------------------
+-- File     : top_topup.vhdl
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity topup_top is
+  port (
+    topup_inTTL    : in  std_logic_vector (1 downto 0);
+    topup_outTTL   : out std_logic_vector (4 downto 0);
+    topup_outPECL  : out std_logic_vector (4 downto 0);
+    -- External clocks
+    topup_CLK25MHz : in  std_logic; -- horloge de 25MHz
+    topup_CLK10Hz  : in  std_logic; -- horloge de 10 Hz
+    -- LED 0 = rouge , 1 = vert
+    topup_LED      : out std_logic_vector (1 downto 0)
+   );
+end entity topup_top;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture rtl_topup_top of topup_top is
+  ------------------------------------------------------------------------------
+  -- constant
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- signal
+  ------------------------------------------------------------------------------
+  signal s_LEDstate   : std_logic;
+  signal s_topupError : std_logic;
+  signal s_IN1        : std_logic;
+  signal s_IN0        : std_logic;
+
+  ------------------------------------------------------------------------------
+  -- Attributes
+  ------------------------------------------------------------------------------
+
+  attribute KEEP : string;
+  attribute KEEP of s_IN0, s_IN1 : signal is "TRUE";
+
+  ------------------------------------------------------------------------------
+  -- Components
+  ------------------------------------------------------------------------------
+  -- Top-up gating
+  -- File : topup_gating.vhdl
+  component topup_gating is
+    port (
+      CLK25MHz   : in  std_logic;
+      CLK10Hz    : in  std_logic;
+      inTTL      : in  std_logic_vector (1 downto 0);
+      outTTL     : out std_logic_vector (4 downto 0);
+      outPECL    : out std_logic_vector (4 downto 0);
+      LEDstate   : out std_logic;
+      topupError : out std_logic
+    );
+  end component topup_gating ;
+
+  -- Top-up LEDS manager
+  -- File : topup_leds.vhdl
+  component topup_leds is
+    port (
+      CLK10Hz    : in  std_logic;
+      LEDstate   : in  std_logic;
+      topupError : in  std_logic;
+      LEDout     : out std_logic_vector (1 downto 0)
+    );
+  end component topup_leds ;
+
+  ------------------------------------------------------------------------------
+  --------------------------------- Main ---------------------------------------
+  ------------------------------------------------------------------------------
+  begin
+
+
+   topup_gating_0 : topup_gating
+    port map (
+      CLK25MHz    => topup_CLK25MHz,
+      CLK10Hz     => topup_CLK10Hz,
+      inTTL(0)    => topup_inTTL(0),
+      inTTL(1)    => s_IN1,
+      outTTL      => topup_outTTL,
+      outPECL     => topup_outPECL,
+      LEDstate    => s_LEDstate,
+      topupError  => s_topupError
+    );
+
+  topup_leds_0 : topup_leds
+    port map (
+      CLK10Hz     => topup_CLK10Hz,
+      LEDstate    => s_LEDstate,
+      topupError  => s_topupError,
+      LEDout      => topup_LED
+    );
+
+  ------------------------------------------------------------------------------
+  ------------------------------------------------------------------------------
+  s_IN0 <= not topup_inTTL(1);
+  s_IN1 <= not s_IN0;
+
+end architecture rtl_topup_top;
+
--- a/fpga/sources/top.vhdl
+++ b/fpga/sources/top.vhdl
--- a/fpga/sources/top_outputmux.vhdl
+++ b/fpga/sources/top_outputmux.vhdl
+--------------------------------------------------------------------------------
+-- Title   : Output Mutiplexer
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : Output multiplexer
+--  SW 5-4-3-2-1-0
+--     0-0-0-0-0-1 : top-up trigger
+--     0-0-0-0-0-0 : duplication
+--------------------------------------------------------------------------------
+-- File     : top_outputmux.vhdl
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity top_outputMux is
+  port (
+    -- Duplication block
+    dup_outTTL    : in std_logic_vector (4 downto 0);
+    dup_outPECL   : in std_logic_vector (4 downto 0);
+    dup_LED       : in std_logic_vector (1 downto 0);
+    -- Top-up block
+    topup_outTTL  : in std_logic_vector (4 downto 0);
+    topup_outPECL : in std_logic_vector (4 downto 0);
+    topup_LED     : in std_logic_vector (1 downto 0);
+    -- Frequency synthesizer block
+    freqsynth_outTTL  : in  std_logic_vector (4 downto 0);
+    freqsynth_outPECL : in  std_logic_vector (4 downto 0);
+    freqsynth_LED     : in  std_logic_vector (1 downto 0);
+    -- Demux for DISCO's spectroscope
+    demuxdisco_outTTL  : in  std_logic_vector (4 downto 0);
+    demuxdisco_outPECL : in  std_logic_vector (4 downto 0);
+    demuxdisco_LED     : in  std_logic_vector (1 downto 0);
+    -- Mux block
+    mux_SWsel     : in  std_logic_vector (5 downto 0);
+    mux_outTTL    : out std_logic_vector (4 downto 0);
+    mux_outPECL   : out std_logic_vector (4 downto 0);
+    mux_outLED    : out std_logic_vector (1 downto 0)
+  );
+end entity top_outputMux;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture rtl_top_outputMux of top_outputMux is
+  ------------------------------------------------------------------------------
+  -- constant
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- signal
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- Components
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  --------------------------------- Main ---------------------------------------
+  ------------------------------------------------------------------------------
+  begin
+
+  with mux_SWsel select
+    mux_outTTL <=
+      topup_outTTL      when "000001",
+      freqsynth_outTTL  when "000010",
+      demuxdisco_outTTL when "000011",
+      dup_outTTL        when OTHERS;
+
+  with mux_SWsel select
+    mux_outPECL <=
+      topup_outPECL      when "000001",
+      freqsynth_outPECL  when "000010",
+      demuxdisco_outPECL when "000011",
+      dup_outPECL        when OTHERS;
+
+  with mux_SWsel select
+    mux_outLED <=
+      topup_LED      when "000001",
+      freqsynth_LED  when "000010",
+      demuxdisco_LED when "000011",
+      dup_LED        when OTHERS;
+
+  ------------------------------------------------------------------------------
+  ------------------------------------------------------------------------------
+end architecture rtl_top_outputMux;
+
--- a/fpga/sources/top_reset.vhdl
+++ b/fpga/sources/top_reset.vhdl
+--------------------------------------------------------------------------------
+-- Title   : RESET
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : Reset
+--------------------------------------------------------------------------------
+-- File     : top_reset.vhd
+-- Revision : 1.0.0
+-- Created  : October 26, 2012
+-- Updated  : October 26, 2012
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity top_reset is
+  port (
+    reset : out std_logic
+  );
+end top_reset;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture rtl_top_reset of top_reset is
+  ------------------------------------------------------------------------------
+  -- constant
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- signal
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- Components
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  --------------------------------- Main ---------------------------------------
+  ------------------------------------------------------------------------------
+  begin
+  -- !!! SET TO 0 AT POWER ON !!!
+  reset <= '0';
+
+end rtl_top_reset;
--- a/readme.txt
+++ b/readme.txt
@@ -7,11 +7,10 @@ This board is based on a Spartan6 FPGA and PLX PCI9030 PCI interface.

 ------------------------
 License:
-The TimEX3 board is released under CERN OHL license (see http://www.ohwr.org).
+The TimEX3 board and corresponding documents are released under CERN OHL license (see http://www.ohwr.org).
 The KiCad libraries for the board are available on Github (https://github.com/Synchrotron-SOLEIL/KiCad-Lib).
 The KiCad libraries are released under GNU GPL version 2 licence (see http://www.kicad-pcb.org/).
 The VHDL codes are released under GNU LGPL licence version 3 licence (see http://www.gnu.org/licenses/lgpl.html).
-The documentations are released under Creative Commons CC BY-ND 3.0 licence (see http://creativecommons.org/).
 Synchrotron SOLEIL's name and logo cannot be used without permission.

 ------------------------